From patchwork Mon Mar 31 12:26:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Bultel X-Patchwork-Id: 14033580 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4C0A41E834F; Mon, 31 Mar 2025 12:28:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743424115; cv=none; b=fyRguIBboKJ7ILZ0qGmHrREA1sifX38FwmD+gNR9o0xPsXQhRf4cl6QIM9tRPc0mc7P0wRyM7Q2AYk3ayy+Y5gr4DXu+gTdjII08WK6LM0iz8ddihgfPDOYL6meH8G4okomJskYNpS9b88unZUzHcY9aWOTvWj1Qv1KrFjr8RgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743424115; c=relaxed/simple; bh=GWielf7pWpaYDnb/1WELPQPrOBhCyIofD7YI2hKn04s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BLTDFyer1OxAt2W5FKyzH8NsxSIBf0GgmTXiRAPNl99U9kNVKjnBeFcffiv3KN/Vg+Jl8SV/qTP2lwRyj7zrBJjGeKuxlmfFUeSD4b82QyWGnke06CgCedNIBUd90rn0bgCJtGHiwWmeiPUhi5a0uuNwGSEPXvZeHCeI586UTyg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: JKFKKMIsSwCEgEhMvdXhLw== X-CSE-MsgGUID: NN3ypOSVSMarB4vtjgFePg== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 31 Mar 2025 21:28:34 +0900 Received: from superbuilder.administration.lan (unknown [10.226.93.144]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id EEBB541F5814; Mon, 31 Mar 2025 21:28:30 +0900 (JST) From: Thierry Bultel To: thierry.bultel@linatsea.fr Cc: linux-renesas-soc@vger.kernel.org, geert@linux-m68k.org, paul.barker.ct@bp.renesas.com, Thierry Bultel , Wolfram Sang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 13/13] arm64: defconfig: Enable Renesas RZ/T2H serial SCI Date: Mon, 31 Mar 2025 14:26:54 +0200 Message-ID: <20250331122657.3390355-14-thierry.bultel.yh@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250331122657.3390355-1-thierry.bultel.yh@bp.renesas.com> References: <20250331122657.3390355-1-thierry.bultel.yh@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Selects RZ/T2H (aka r9a09g077) SCI (serial) specific code. Reviewed-by: Wolfram Sang Signed-off-by: Thierry Bultel --- Changes v5->v6: - Renamed CONFIG_SERIAL_RZ_SCI_T2 to CONFIG_SERIAL_RSCI Changes v4->v5: - Renamed CONFIG_SERIAL_RZ_SCI to CONFIG_SERIAL_RZ_SCI_T2 Changes v3->v4: - Remove CONFIG_ARCH_R9A09G077=y --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..fcfc7b2e5819 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -494,6 +494,7 @@ CONFIG_SERIAL_TEGRA_TCU=y CONFIG_SERIAL_IMX=y CONFIG_SERIAL_IMX_CONSOLE=y CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_RSCI=y CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_QCOM_GENI=y