From patchwork Thu Jun 20 13:57:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13705568 X-Patchwork-Delegate: geert@linux-m68k.org Received: from andre.telenet-ops.be (andre.telenet-ops.be [195.130.132.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 882D51AE85D for ; Thu, 20 Jun 2024 13:57:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718891878; cv=none; b=bN9B+pb/CakEDLKDGmLPN4/gAbzdkJqe6W9MfBUw1CWqOnfhNkH2HrKcZ76pro396BpLmcaKYvDxd85nyU5jRj6+S60ItYbWurmTAi6EijcASbEysMvaN+WgqTshGZmyJnwfZRbpo6aZgNWzl40xrOnCbDzeBwACt89A48VQ4tk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718891878; c=relaxed/simple; bh=HW02G0GzSgkc5j8kPzEVYxFX415b95zPttIFlHDJ4vc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kZseL9BKOIMaeW5wsxZLoHhJFukC0H4b1bhPW9rirKAzJy7SZIbZZkN4JLjfZS/N34sXFlOzuGpnLv7k5d6JR+Io3zgBI7C8Rq/jjy+BcjzOjQ0JyEmOas9q6LO6dEg1akh3cGpkvDGjrqa1MbxZxDCjuHr+dIngw+7iCKlst0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:260f:cd5c:91b1:523c]) by andre.telenet-ops.be with bizsmtp id dpxm2C0030Y0hZi01pxmJR; Thu, 20 Jun 2024 15:57:48 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1sKIIM-000586-1h; Thu, 20 Jun 2024 15:57:46 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1sKIIL-000Cp5-Vl; Thu, 20 Jun 2024 15:57:45 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda , Lad Prabhakar , Biju Das , Claudiu Beznea Cc: Mark Rutland , Marc Zyngier , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/9] arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQ Date: Thu, 20 Jun 2024 15:57:35 +0200 Message-Id: <21f556eb7e903d5b9f4c96188fd4b6ae0db71856.1718890849.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 68a45525297b2e9a ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's") Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index c07ddd8124e6804c..d3838e5820fca19f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1334,6 +1334,9 @@ timer { interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; };