From patchwork Tue Mar 28 14:41:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13191158 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD810C76196 for ; Tue, 28 Mar 2023 14:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232965AbjC1OmI (ORCPT ); Tue, 28 Mar 2023 10:42:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230197AbjC1OmH (ORCPT ); Tue, 28 Mar 2023 10:42:07 -0400 Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAD2286A5 for ; Tue, 28 Mar 2023 07:42:00 -0700 (PDT) Received: from ramsan.of.borg ([84.195.187.55]) by albert.telenet-ops.be with bizsmtp id dqhy2900X1C8whw06qhyg2; Tue, 28 Mar 2023 16:41:59 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1phAVf-00F96K-5F; Tue, 28 Mar 2023 16:41:58 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1phAWM-006GAq-Mw; Tue, 28 Mar 2023 16:41:58 +0200 From: Geert Uytterhoeven To: Magnus Damm , Marek Vasut , Yoshihiro Shimoda Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC 2/2] ARM: dts: marzen: Add PCIe support Date: Tue, 28 Mar 2023 16:41:57 +0200 Message-Id: <31ebd1e07dd28e1bf36dee5ec4a918b0edf5cbb2.1680012171.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Describe the PCIe bus clock, and enable the PCIe controller on the Marzen development board. Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7779-marzen.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 632519edba6b5a47..a001e4285fd76366 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -260,6 +260,14 @@ &tmu0 { status = "okay"; }; +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default";