From patchwork Tue Nov 6 18:52:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10671327 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1846C109C for ; Tue, 6 Nov 2018 19:22:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 029162B1B2 for ; Tue, 6 Nov 2018 19:22:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EAD0C2B1B3; Tue, 6 Nov 2018 19:22:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C09F2B1B9 for ; Tue, 6 Nov 2018 19:22:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387862AbeKGEsw (ORCPT ); Tue, 6 Nov 2018 23:48:52 -0500 Received: from mail-lf1-f66.google.com ([209.85.167.66]:46111 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387700AbeKGEsv (ORCPT ); Tue, 6 Nov 2018 23:48:51 -0500 Received: by mail-lf1-f66.google.com with SMTP id f23so5168732lfc.13 for ; Tue, 06 Nov 2018 11:22:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=82ZMIjYcs1B4Wui1k7Dl7syqB2XJmE+k6h0at1eAo/Y=; b=ghXqLHI9QdRURXXw4H//HJ/FBsyNZ70MbrVqImuFhcqGnHH89RuNz9kpa5F7/si7h4 GYDIdwNRDc7fvn+t463RGXrMuwm9o7+WNE/Tyjq/WOZaEV3FMudAPRXQIc4NNTIeSBKE 8a6ddq3VDpG/OIp+Y/6dSUG1qgeTjh4Obk5ZJALiK6mf/XEmDVD1q81okYXszfKAa6t/ skl5opnSVHZREMZN5gzi/+vuAmYfL4BeGj7ldNzNIN2tpS3XGSHuKKkc1ngXlv7oloEY FhYabB1zXaulRpPbTTO6vYqlGKxPLNmDrjFJQf7eJvNQRINtxUNJBmFfL+VGqodhl/LA XOvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=82ZMIjYcs1B4Wui1k7Dl7syqB2XJmE+k6h0at1eAo/Y=; b=oFXjQ9S2IJ5heXrySACwNZxFBiGJPhk1ECw1ATyF8csCR3QhmPJ+GvyADKlGqDkbi7 5scCDp2aw3QQnGPjA0+baMqlMpTGzbGM77Nj81oPyx88yD2kyikaxbYScn2IXJFj81WT HhRQ+Gigb/xd9WWTvnJxj3c1ZCJadNpK6I/rbjX/8PfNzRnx3aDqPVfvZo3UDXmt8hS9 96CyWZof4sSc7NbG0FcUXp4PyUBvcvvkOFGbBlXx6Yzhium0R6igodRZiapvl+4WOcIh ucJePG+/Qw8ZhoYOgENyobFfufpPYhlHAM8iK02aVeU7c+mn9nAoKyg4zhtt+F8Dhe7o ipjg== X-Gm-Message-State: AGRZ1gKNv1hgk1j6YM/Yd7qWMcZxkRi6J8ADfYx7MDQt4C6Ch2r1UM/c 7ABfSekaSQteAw6Nv4Uyu9I8cH95Uns= X-Google-Smtp-Source: AJdET5dfN7F7AAJQAhNNf0OwNqJ3jsDkC+rd7UF508SitxjYNB5Ba81VxhIdO+1l6Z0AuH0BbVMtZw== X-Received: by 2002:a19:d295:: with SMTP id j143mr15630225lfg.50.1541530378826; Tue, 06 Nov 2018 10:52:58 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.83.173]) by smtp.gmail.com with ESMTPSA id y1-v6sm2898617ljh.39.2018.11.06.10.52.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Nov 2018 10:52:58 -0800 (PST) From: Sergei Shtylyov Subject: [PATCH] pinctrl: sh-pfc: r8a77970: add QSPI pins, groups, and functions To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: <38b17a18-59d6-3fbf-8413-915005b274f6@cogentembedded.com> Date: Tue, 6 Nov 2018 21:52:55 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dmitry Shifrin Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin Signed-off-by: Sergei Shtylyov Reviewed-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo. drivers/pinctrl/sh-pfc/pfc-r8a77970.c | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -1382,6 +1382,56 @@ static const unsigned int pwm4_b_mux[] = PWM4_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -1756,6 +1806,12 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data), @@ -1950,6 +2006,18 @@ static const char * const pwm4_groups[] "pwm4_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif_clk_groups[] = { "scif_clk_a", "scif_clk_b", @@ -2033,6 +2101,8 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),