From patchwork Thu Feb 11 15:57:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robin Murphy X-Patchwork-Id: 8281891 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1477ABEEE5 for ; Thu, 11 Feb 2016 15:57:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 60F142035D for ; Thu, 11 Feb 2016 15:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9D6D82034C for ; Thu, 11 Feb 2016 15:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751172AbcBKP5b (ORCPT ); Thu, 11 Feb 2016 10:57:31 -0500 Received: from foss.arm.com ([217.140.101.70]:55634 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750889AbcBKP5a (ORCPT ); Thu, 11 Feb 2016 10:57:30 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 56C5949; Thu, 11 Feb 2016 07:56:42 -0800 (PST) Received: from [10.1.205.42] (e104324-lin.cambridge.arm.com [10.1.205.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CAAE03F25E; Thu, 11 Feb 2016 07:57:27 -0800 (PST) Subject: Re: [PATCH v3 1/8] iommu: Add MMIO mapping type To: Laurent Pinchart , =?UTF-8?Q?Niklas_S=c3=b6derlund?= References: <1455065878-11906-1-git-send-email-niklas.soderlund+renesas@ragnatech.se> <1455065878-11906-2-git-send-email-niklas.soderlund+renesas@ragnatech.se> <13740597.5lZXKsEG19@avalon> Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, iommu@lists.linux-foundation.org, vinod.koul@intel.com, geert+renesas@glider.be, linus.walleij@linaro.org, dan.j.williams@intel.com, arnd@arndb.de, linux-arch@vger.kernel.org From: Robin Murphy Message-ID: <56BCAF66.8010206@arm.com> Date: Thu, 11 Feb 2016 15:57:26 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <13740597.5lZXKsEG19@avalon> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 11/02/16 00:02, Laurent Pinchart wrote: > Hi Niklas, > > Thank you for the patch. > > On Wednesday 10 February 2016 01:57:51 Niklas Söderlund wrote: >> From: Robin Murphy >> >> On some platforms, MMIO regions might need slightly different treatment >> compared to mapping regular memory; add the notion of MMIO mappings to >> the IOMMU API's memory type flags, so that callers can let the IOMMU >> drivers know to do the right thing. >> >> Signed-off-by: Robin Murphy >> Acked-by: Laurent Pinchart > > Answering the question from the cover letter, yes, it's totally fine to pick > the ack, that's actually expected. > >> --- >> drivers/iommu/io-pgtable-arm.c | 4 +++- >> include/linux/iommu.h | 1 + > > You might be asked to split this patch in two. Worse than that, you might also be asked to fix it up when the silly author remembers that he did this on a stage-2-only ARM SMMU, and the attributes for the stage 1 tables that the IPMMU uses are in a different code path: --->8--- } else { --->8--- Sorry for the bother, Robin. >> 2 files changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c >> index 381ca5a..3ff4f87 100644 >> --- a/drivers/iommu/io-pgtable-arm.c >> +++ b/drivers/iommu/io-pgtable-arm.c >> @@ -364,7 +364,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct >> arm_lpae_io_pgtable *data, pte |= ARM_LPAE_PTE_HAP_READ; >> if (prot & IOMMU_WRITE) >> pte |= ARM_LPAE_PTE_HAP_WRITE; >> - if (prot & IOMMU_CACHE) >> + if (prot & IOMMU_MMIO) >> + pte |= ARM_LPAE_PTE_MEMATTR_DEV; >> + else if (prot & IOMMU_CACHE) >> pte |= ARM_LPAE_PTE_MEMATTR_OIWB; >> else >> pte |= ARM_LPAE_PTE_MEMATTR_NC; >> diff --git a/include/linux/iommu.h b/include/linux/iommu.h >> index a5c539f..34b6432 100644 >> --- a/include/linux/iommu.h >> +++ b/include/linux/iommu.h >> @@ -30,6 +30,7 @@ >> #define IOMMU_WRITE (1 << 1) >> #define IOMMU_CACHE (1 << 2) /* DMA cache coherency */ >> #define IOMMU_NOEXEC (1 << 3) >> +#define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */ >> >> struct iommu_ops; >> struct iommu_group; > diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 5b5c299..7622c6e 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -354,7 +354,10 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) pte |= ARM_LPAE_PTE_AP_RDONLY; - if (prot & IOMMU_CACHE) + if (prot & IOMMU_MMIO) + pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV + << ARM_LPAE_PTE_ATTRINDX_SHIFT); + else if (prot & IOMMU_CACHE) pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE << ARM_LPAE_PTE_ATTRINDX_SHIFT);