From patchwork Fri Feb 12 19:05:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 8296001 Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 32B72C02AA for ; Fri, 12 Feb 2016 19:07:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8375B20225 for ; Fri, 12 Feb 2016 19:07:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B2CE620452 for ; Fri, 12 Feb 2016 19:07:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751002AbcBLTHc (ORCPT ); Fri, 12 Feb 2016 14:07:32 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:41775 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750928AbcBLTHc (ORCPT ); Fri, 12 Feb 2016 14:07:32 -0500 Received: from penelope.kanocho.kobe.vergenet.net (128-47-71-217.dyn.estpak.ee [217.71.47.128]) by kirsty.vergenet.net (Postfix) with ESMTPSA id 28C1425BEE1; Sat, 13 Feb 2016 06:06:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1455304007; bh=N3yHWnyUP0gA7Fi2vsatjsVUJcdnnA28yNjz169mmxU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=da0YBuIqAxyPBERsLBJHDDYAujvCr+i4SUOqMVj0555xgnlzK2545yXrycw2cYHp+ FHlfvRtYCMpaVIm+gYi+kr8KZwvPyq6Ou0kTZw0SqzolOAPWJmigUnEZZ3QdRPhDL+ X6LV5bBahlxa3n2PXYfdLxADX9aSUCAuKdrS/BN0= Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id 2970561167; Sat, 13 Feb 2016 06:06:11 +1100 (AEDT) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 55/68] ARM: dts: r8a7778: Add BRG support for SCIF Date: Fri, 12 Feb 2016 20:05:45 +0100 Message-Id: <5fb544da5f9a77ef723b685181d4e763f6a1b2eb.1455303422.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7778.dtsi | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 50784e2b632d..f83a348fc07a 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -301,8 +301,9 @@ "renesas,scif"; reg = <0xffe40000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF0>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -312,8 +313,9 @@ "renesas,scif"; reg = <0xffe41000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF1>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -323,8 +325,9 @@ "renesas,scif"; reg = <0xffe42000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF2>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -334,8 +337,9 @@ "renesas,scif"; reg = <0xffe43000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF3>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -345,8 +349,9 @@ "renesas,scif"; reg = <0xffe44000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF4>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -356,8 +361,9 @@ "renesas,scif"; reg = <0xffe45000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7778_CLK_SCIF5>, + <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -444,6 +450,15 @@ clock-output-names = "extal"; }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@ffc80000 { compatible = "renesas,r8a7778-cpg-clocks";