From patchwork Thu Feb 4 14:29:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 8223201 Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BF0D29FE7F for ; Thu, 4 Feb 2016 14:32:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0848F201D3 for ; Thu, 4 Feb 2016 14:32:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2D5342038F for ; Thu, 4 Feb 2016 14:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757685AbcBDObX (ORCPT ); Thu, 4 Feb 2016 09:31:23 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:49245 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754220AbcBDObX (ORCPT ); Thu, 4 Feb 2016 09:31:23 -0500 Received: from penelope.kanocho.kobe.vergenet.net (d54c0ad22.access.telenet.be [84.192.173.34]) by kirsty.vergenet.net (Postfix) with ESMTPSA id 2645525BF00; Fri, 5 Feb 2016 01:30:25 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1454596225; bh=jyg0PIBl8EjUb2sjE7yCNXfv6y8G4lMTIihgU2VVQbQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j0CxNl9t+/JE6hGqjkMZqTqGQCDSUCrOQQtUBmvoQXauG9HMVdovWl7hSaXZnV6Gb 9zoPrvGvBdqN5mPTJuJvU0SIVchz5YD/d390bhR9vHOOr2y0EyWXGwhrRrU4Fbmzxp Nj2hF12jJ8Fny773X0xsIZAZzH6mAdS3HpCUex20= Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id AF84861005; Fri, 5 Feb 2016 01:30:05 +1100 (AEDT) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 58/70] ARM: dts: r8a7779: Add BRG support for SCIF Date: Thu, 4 Feb 2016 15:29:52 +0100 Message-Id: <746a135be6849eb52db2bd6db6e0fa57912c6fd4.1454595846.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add the device node for the external SCIF_CLK. The presence of the SCIF_CLK crystal and its clock frequency depends on the actual board. Add the two optional clock sources (S1 and SCIF_CLK for the internal resp. external clock) for the Baud Rate Generator for External Clock (BRG) to all SCIF device nodes. This increases the range and accuracy of supported baud rates on SCIF. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7779.dtsi | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 8fddfae13865..a0cc08e6295b 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -215,8 +215,9 @@ "renesas,scif"; reg = <0xffe40000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -226,8 +227,9 @@ "renesas,scif"; reg = <0xffe41000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -237,8 +239,9 @@ "renesas,scif"; reg = <0xffe42000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -248,8 +251,9 @@ "renesas,scif"; reg = <0xffe43000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -259,8 +263,9 @@ "renesas,scif"; reg = <0xffe44000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -270,8 +275,9 @@ "renesas,scif"; reg = <0xffe45000 0x100>; interrupts = ; - clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; - clock-names = "fck"; + clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, + <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -447,6 +453,15 @@ clock-output-names = "extal"; }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: clocks@ffc80000 { compatible = "renesas,r8a7779-cpg-clocks";