| Message ID | 7731111c9e383c41173ac08f3a040a18449ac542.1712207606.git.ysato@users.sourceforge.jp (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [RESEND,v7,01/37] sh: passing FDT address to kernel startup. | expand |
On Thu, Apr 04, 2024 at 02:14:36PM +0900, Yoshinori Sato wrote: > Renesas SH series and compatible ISA CPUs. > > Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> > --- > .../devicetree/bindings/sh/cpus.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml > > diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml > new file mode 100644 > index 000000000000..9e5640793d76 > --- /dev/null > +++ b/Documentation/devicetree/bindings/sh/cpus.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/sh/cpus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas SuperH CPUs > + > +maintainers: > + - Yoshinori Sato <ysato@users.sourceforge.jp> > + > +description: |+ > + Definition of CPU core with Renesas SuperH and compatible instruction set. > + > +properties: > + compatible: > + anyOf: oneOf > + - items: > + - enum: > + - renesas,sh2a > + - renesas,sh3 > + - renesas,sh4 > + - renesas,sh4a > + - jcore,j2 > + - const: renesas,sh2 > + - const: renesas,sh2 > + > + clocks: > + maxItems: 1 > + > + reg: > + maxItems: 1 > + > + device_type: > + const: cpu > + > +required: > + - compatible > + - reg > + - device_type > + > +additionalProperties: true This is a problem with the other cpu bindings, but should not be copied here. Add a $ref to schemas/cpu.yaml and make this 'unevaluatedProperties: false'. > + > +examples: > + - | > + #include <dt-bindings/clock/sh7750-cpg.h> > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu: cpu@0 { > + compatible = "renesas,sh4", "renesas,sh2"; > + device_type = "cpu"; > + reg = <0>; > + clocks = <&cpg SH7750_CPG_ICK>; > + clock-names = "ick"; > + icache-size = <16384>; > + icache-line-size = <32>; > + dcache-size = <32768>; > + dcache-line-size = <32>; > + }; > + }; > +... > -- > 2.39.2 >
diff --git a/Documentation/devicetree/bindings/sh/cpus.yaml b/Documentation/devicetree/bindings/sh/cpus.yaml new file mode 100644 index 000000000000..9e5640793d76 --- /dev/null +++ b/Documentation/devicetree/bindings/sh/cpus.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sh/cpus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas SuperH CPUs + +maintainers: + - Yoshinori Sato <ysato@users.sourceforge.jp> + +description: |+ + Definition of CPU core with Renesas SuperH and compatible instruction set. + +properties: + compatible: + anyOf: + - items: + - enum: + - renesas,sh2a + - renesas,sh3 + - renesas,sh4 + - renesas,sh4a + - jcore,j2 + - const: renesas,sh2 + - const: renesas,sh2 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + + device_type: + const: cpu + +required: + - compatible + - reg + - device_type + +additionalProperties: true + +examples: + - | + #include <dt-bindings/clock/sh7750-cpg.h> + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; +...
Renesas SH series and compatible ISA CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> --- .../devicetree/bindings/sh/cpus.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/sh/cpus.yaml