| Message ID | 8735fltxwg.wl-kuninori.morimoto.gx@renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | pinctrl: renesas: r8a779g0: Add pins, groups and functions | expand |
Hi Morimoto-san, On Fri, Jul 1, 2022 at 3:38 AM Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx, > GP1_23 - GP1_28 are 1.8/3.3V. But it aren't on Table 7.28. > According to HW team, there are no bit assign. > This patch follows HW team's comment. > > Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Thanks for your patch! > --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c > +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c > @@ -17,7 +17,14 @@ > > #define CPU_ALL_GP(fn, sfx) \ > PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ > - PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ > + PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ > + PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \ > + PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \ Oops, one pin too many (29 != 23 + 7). The checker would have told you: Pin 61 is not in bias info list WARNING: CPU: 3 PID: 1 at drivers/pinctrl/renesas/pinctrl.c:852 rcar_pin_to_bias_reg+0x54/0xa0 .... r8a779g0_pfc: pin GP_1_29: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs r8a779g0_pfc: pin GP_1_29: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs r8a779g0_pfc: pin GP_1_29: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs > PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \ > PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ > PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ > @@ -3650,7 +3657,7 @@ static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) > return bit; > > *pocctrl = pinmux_ioctrl_regs[POC1].reg; > - if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 28)) > + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) > return bit; > > *pocctrl = pinmux_ioctrl_regs[POC3].reg; The rest is fine, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.20, with the offending line dropped. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 70ca971bbf36..281bca886307 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -17,7 +17,14 @@ #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ - PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_1(1, 29, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_13(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ @@ -3650,7 +3657,7 @@ static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) return bit; *pocctrl = pinmux_ioctrl_regs[POC1].reg; - if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 28)) + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22)) return bit; *pocctrl = pinmux_ioctrl_regs[POC3].reg;