| Message ID | 8737rrfe1f.wl%kuninori.morimoto.gx@renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
Hi Morimoto-san, On Wed, Mar 16, 2016 at 1:48 AM, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > Gen2 / Gen3 datasheet will have below note in next version. > This patch follows this note. > > IPSRx and MOD_SELx registers shall be set before setting GPSRx > registers in case that they need to be configured. > MOD_SELx registers can be set either earlier or later than setting > IPSRx registers. Does this note apply to R-Car Gen1 and SH7734, too? Both use the PINMUX_IPSR_MSEL() macro. > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > --- > drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h > index 2b593fc..f174d61 100644 > --- a/drivers/pinctrl/sh-pfc/sh_pfc.h > +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h > @@ -279,7 +279,7 @@ struct sh_pfc_soc_info { > * - msel: Module selector > */ > #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ > - PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn) > + PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert > > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > > > Gen2 / Gen3 datasheet will have below note in next version. > > This patch follows this note. > > > > IPSRx and MOD_SELx registers shall be set before setting GPSRx > > registers in case that they need to be configured. > > MOD_SELx registers can be set either earlier or later than setting > > IPSRx registers. > > Does this note apply to R-Car Gen1 and SH7734, too? > Both use the PINMUX_IPSR_MSEL() macro. Yes, this note can be match for these. But I'm not sure whether these datasheet will be updated.
Hi Morimoto-san, Thank you for the patch. On Wednesday 16 March 2016 00:48:11 Kuninori Morimoto wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > Gen2 / Gen3 datasheet will have below note in next version. > This patch follows this note. > > IPSRx and MOD_SELx registers shall be set before setting GPSRx > registers in case that they need to be configured. > MOD_SELx registers can be set either earlier or later than setting > IPSRx registers. > > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > drivers/pinctrl/sh-pfc/sh_pfc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h > b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2b593fc..f174d61 100644 > --- a/drivers/pinctrl/sh-pfc/sh_pfc.h > +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h > @@ -279,7 +279,7 @@ struct sh_pfc_soc_info { > * - msel: Module selector > */ > #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ > - PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn) > + PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) > > /* > * Describe a pinmux configuration for a single-function pin with GPIO
On Wed, Mar 16, 2016 at 1:48 AM, Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> wrote: > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > Gen2 / Gen3 datasheet will have below note in next version. > This patch follows this note. > > IPSRx and MOD_SELx registers shall be set before setting GPSRx > registers in case that they need to be configured. > MOD_SELx registers can be set either earlier or later than setting > IPSRx registers. > > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> I wait for Geert to either queue this for his first v4.7 pull request or tell me to apply it for fixes. Is it a regression? Yours, Linus Walleij
Hi Linus, On Tue, Mar 22, 2016 at 2:18 PM, Linus Walleij <linus.walleij@linaro.org> wrote: > On Wed, Mar 16, 2016 at 1:48 AM, Kuninori Morimoto > <kuninori.morimoto.gx@renesas.com> wrote: > >> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> >> >> Gen2 / Gen3 datasheet will have below note in next version. >> This patch follows this note. >> >> IPSRx and MOD_SELx registers shall be set before setting GPSRx >> registers in case that they need to be configured. >> MOD_SELx registers can be set either earlier or later than setting >> IPSRx registers. >> >> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> > > I wait for Geert to either queue this for his first v4.7 pull request > or tell me to apply it for fixes. Is it a regression? I'm not aware of any issues due to this. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Tue, Mar 22, 2016 at 3:30 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Tue, Mar 22, 2016 at 2:18 PM, Linus Walleij <linus.walleij@linaro.org> wrote: >> I wait for Geert to either queue this for his first v4.7 pull request >> or tell me to apply it for fixes. Is it a regression? > > I'm not aware of any issues due to this. OK just queue it with the rest. I assume there will still be lots of action in sh-pfc for this merge window. Yours, Linus Walleij
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 2b593fc..f174d61 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -279,7 +279,7 @@ struct sh_pfc_soc_info { * - msel: Module selector */ #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ - PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn) + PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) /* * Describe a pinmux configuration for a single-function pin with GPIO