[v3,1/3] clk: renesas: r8a77995: Add ZA2 clock

Commit Message

Kuninori Morimoto May 27, 2021, 4:36 a.m. UTC

From: Kuninori Morimoto <[e-mail]>

R-Car D3 ZA2 clock is from PLL0D3 or S0,
and it can be controlled by ZA2CKCR.
It is needed for R-Car Sound, but is not used so far.
Using default settings is very enough at this point.
This patch adds it by DEF_FIXED().

Link: https://lore.kernel.org/r/[e-mail]
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Kuninori Morimoto <[e-mail]>
---
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Geert Uytterhoeven May 27, 2021, 9:12 a.m. UTC | #1

On Thu, May 27, 2021 at 6:36 AM Kuninori Morimoto
<[e-mail]> wrote:
> From: Kuninori Morimoto <[e-mail]>
>
> R-Car D3 ZA2 clock is from PLL0D3 or S0,
> and it can be controlled by ZA2CKCR.
> It is needed for R-Car Sound, but is not used so far.
> Using default settings is very enough at this point.
> This patch adds it by DEF_FIXED().
>
> Link: https://lore.kernel.org/r/[e-mail]
> Link: https://lore.kernel.org/r/[e-mail]
> Signed-off-by: Kuninori Morimoto <[e-mail]>

Reviewed-by: Geert Uytterhoeven <[e-mail]>
i.e. will queue in renesas-clk-for-v5.14.

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 9cfd00cf4e69..81c0bc1e78af 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -75,6 +75,7 @@  static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
 	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
 
 	/* Core Clock Outputs */
+	DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,     2, 1),
 	DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
 	DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
 	DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),