diff mbox series

[3/4] clk: renesas: r8a779g0: Add Audio clocks

Message ID 87tu0et4up.wl-kuninori.morimoto.gx@renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: V4H Sound support | expand

Commit Message

Kuninori Morimoto Jan. 26, 2023, 2:19 a.m. UTC 
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

This patch adds module clocks for Audio (SSI/SSIU) blocks on
the Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Geert Uytterhoeven Jan. 26, 2023, 1:56 p.m. UTC | #1 
Hi Morimoto-san,

On Thu, Jan 26, 2023 at 3:19 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds module clocks for Audio (SSI/SSIU) blocks on
> the Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -202,6 +202,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
>         DEF_MOD("pfc1",         916,    R8A779G0_CLK_CL16M),
>         DEF_MOD("pfc2",         917,    R8A779G0_CLK_CL16M),
>         DEF_MOD("pfc3",         918,    R8A779G0_CLK_CL16M),
> +       DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),
> +       DEF_MOD("ssi",          2927,   R8A779G0_CLK_S0D6_PER),

LGTM, although I couldn't verify the parent clock.

>  };

Does this actually work as-is?
The arrays in drivers/clk/renesas/renesas-cpg-mssr.c do not yet contain
the register offsets for e.g. MSTPCR28 and beyond...

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Kuninori Morimoto Jan. 27, 2023, 4:25 a.m. UTC | #2 
Hi Geert

> Does this actually work as-is?
> The arrays in drivers/clk/renesas/renesas-cpg-mssr.c do not yet contain
> the register offsets for e.g. MSTPCR28 and beyond...

Thank you for pointing it.
I needs extra patch.

I will re-check and post the patches again.

Thank you for your help !!

Best regards
---
Kuninori Morimoto
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index c6337a408e5e..1c95aa1cd07e 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -202,6 +202,8 @@  static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),
 	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),
 	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CL16M),
+	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),
+	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),
 };
 
 /*