From patchwork Thu Jun 20 13:57:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13705564 X-Patchwork-Delegate: geert@linux-m68k.org Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [195.130.132.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 969C91AE0BD for ; Thu, 20 Jun 2024 13:57:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.130.132.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718891873; cv=none; b=U6p3okEc2ixXTkkEL1Iv2mhV1r7RM9Eq+0eBsLP/rBcamDhcf9kxVk+MbLSOvXQsehlieo+//Je7EPT4YZaQkMejDWzSbIG4AyFNeZlDxJg35lxDETzhKWxgxHkxuH4Re4Y2l6Pv8PevrkIAEl6bjgFT3moKrXfUz9cp5oS+LKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718891873; c=relaxed/simple; bh=q2THssTVRN2HRxvvKj3JZmaMW6yjUpcHC6eAvKX7n0Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F7IfVpAQg1dRgkCA6SsculKw33uewxqURiYenFLyMBWkzAgMyI6CF8y+AhBnEoWEjuNAIh+83+xmB8X5Rws2RQzyOouwnIc2QMLkeAPo4edUH2GSEzAhqWnpRR+fzusEYqgimJ17nL/UlreW8NhgfAfg7DK9BjsDJt6B0ktecxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be; spf=none smtp.mailfrom=linux-m68k.org; arc=none smtp.client-ip=195.130.132.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=glider.be Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux-m68k.org Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed80:260f:cd5c:91b1:523c]) by xavier.telenet-ops.be with bizsmtp id dpxm2C00E0Y0hZi01pxm6u; Thu, 20 Jun 2024 15:57:47 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.95) (envelope-from ) id 1sKIIM-00058D-2x; Thu, 20 Jun 2024 15:57:46 +0200 Received: from geert by rox.of.borg with local (Exim 4.95) (envelope-from ) id 1sKIIM-000CpG-13; Thu, 20 Jun 2024 15:57:46 +0200 From: Geert Uytterhoeven To: Magnus Damm , Yoshihiro Shimoda , Lad Prabhakar , Biju Das , Claudiu Beznea Cc: Mark Rutland , Marc Zyngier , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 7/9] arm64: dts: renesas: r9a08g045: Add missing hypervisor virtual timer IRQ Date: Thu, 20 Jun 2024 15:57:37 +0200 Message-Id: <884c683fb6c1d1bf7d0d383a8df8f65a0a424dc7.1718890849.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: e20396d65b959a65 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC") Signed-off-by: Geert Uytterhoeven Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 2162c247d6deb170..0d5c47a65e46c584 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -294,6 +294,9 @@ timer { interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", + "hyp-virt"; }; };