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[1/5] arm64: dts: renesas: r8a779h0: Add L3 cache controller

Message ID 9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be (mailing list archive)
State Mainlined
Commit 48a9cfe6d9f2754eb1709d9658ab309cefa621cb
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: r8a779h0: Add full CA76 CPU core support | expand

Commit Message

Geert Uytterhoeven Feb. 1, 2024, 2:19 p.m. UTC 
From: Duy Nguyen <duy.nguyen.rh@renesas.com>

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Rename L3_CA76_0 label to L3_CA76,
  - Rename cache-controller-0 node to cache-controller.
---
 arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index eb555cbf51a41001..f47695158d991288 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -23,6 +23,14 @@  a76_0: cpu@0 {
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA76>;
+		};
+
+		L3_CA76: cache-controller {
+			compatible = "cache";
+			power-domains = <&sysc R8A779H0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
 		};
 	};