| Message ID | YQGFP/cFoSksPyn+@pendragon.ideasonboard.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | [RESEND,v2,1/2] dt-bindings: display: bridge: Add binding for R-Car MIPI DSI/CSI-2 TX | expand |
On Wed, Jul 28, 2021 at 07:26:39PM +0300, Laurent Pinchart wrote: > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > --- > Looks like I forgot to CC the devicetree mailing list and Rob Herring on > the first try. Resending, sorry about that. > --- > .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 119 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml Reviewed-by: Rob Herring <robh@kernel.org> BTW, b4 doesn't like your message-id.
Hi Rob, On Mon, Aug 02, 2021 at 04:37:38PM -0600, Rob Herring wrote: > On Wed, Jul 28, 2021 at 07:26:39PM +0300, Laurent Pinchart wrote: > > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > --- > > Looks like I forgot to CC the devicetree mailing list and Rob Herring on > > the first try. Resending, sorry about that. > > --- > > .../display/bridge/renesas,dsi-csi2-tx.yaml | 118 ++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 119 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > > Reviewed-by: Rob Herring <robh@kernel.org> > > BTW, b4 doesn't like your message-id. I've told base64, but it shrugged. Is there a recommendation to change mutt's message_id_format from the default ?
Hi Laurent, On Wed, Jul 28, 2021 at 6:26 PM Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> wrote: > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > @@ -0,0 +1,118 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder > + > +maintainers: > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > + > +description: | > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up > + to four data lanes. > + > +properties: > + compatible: > + enum: > + - renesas,r8a779a0-dsi-csi2-tx # for V3U > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Functional clock > + - description: DSI (and CSI-2) functional clock > + - description: PLL reference clock > + > + clock-names: > + items: > + - const: fck > + - const: dsi > + - const: pll No interrupts? The hardware manual says there are 9 interrupts. Gr{oetje,eeting}s, Geert
Hi Geert, On Tue, Sep 21, 2021 at 05:53:52PM +0200, Geert Uytterhoeven wrote: > On Wed, Jul 28, 2021 at 6:26 PM Laurent Pinchart wrote: > > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > > @@ -0,0 +1,118 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder > > + > > +maintainers: > > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > + > > +description: | > > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas > > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up > > + to four data lanes. > > + > > +properties: > > + compatible: > > + enum: > > + - renesas,r8a779a0-dsi-csi2-tx # for V3U > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: Functional clock > > + - description: DSI (and CSI-2) functional clock > > + - description: PLL reference clock > > + > > + clock-names: > > + items: > > + - const: fck > > + - const: dsi > > + - const: pll > > No interrupts? > The hardware manual says there are 9 interrupts. Who comes up with such insanely high numbers of interrupts ? :-) What the hardware manual doesn't document is how interrupts are mapped. There's indeed 9 of them, and there are 9 interrupt sources, but that's all we know. I can easily add a interrupts: maxItems: 9 but I can add interrupt names without additional information. It may be possible to deduce some of the interrupt mappings from experiments, but not all of them. What do you think would be a good way forward ? Leave the interrupts out for now as we don't have the information ? Only list the interrupts but not their names ? Something else ?
Hi Laurent, On Wed, Sep 22, 2021 at 3:27 AM Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Tue, Sep 21, 2021 at 05:53:52PM +0200, Geert Uytterhoeven wrote: > > On Wed, Jul 28, 2021 at 6:26 PM Laurent Pinchart wrote: > > > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > > > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > > > Thanks for your patch! > > > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > > > @@ -0,0 +1,118 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder > > > + > > > +maintainers: > > > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > + > > > +description: | > > > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas > > > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up > > > + to four data lanes. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - renesas,r8a779a0-dsi-csi2-tx # for V3U > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: Functional clock > > > + - description: DSI (and CSI-2) functional clock > > > + - description: PLL reference clock > > > + > > > + clock-names: > > > + items: > > > + - const: fck > > > + - const: dsi > > > + - const: pll > > > > No interrupts? > > The hardware manual says there are 9 interrupts. > > Who comes up with such insanely high numbers of interrupts ? :-) > > What the hardware manual doesn't document is how interrupts are mapped. > There's indeed 9 of them, and there are 9 interrupt sources, but that's > all we know. I can easily add a > > interrupts: > maxItems: 9 > > but I can add interrupt names without additional information. It may be > possible to deduce some of the interrupt mappings from experiments, but > not all of them. What do you think would be a good way forward ? Leave > the interrupts out for now as we don't have the information ? Only list > the interrupts but not their names ? Something else ? I think what we did in the past is not list the interrupts at all. They can be added once we receive more documentation. Gr{oetje,eeting}s, Geert
Hi Geert, On Wed, Sep 22, 2021 at 08:43:57AM +0200, Geert Uytterhoeven wrote: > On Wed, Sep 22, 2021 at 3:27 AM Laurent Pinchart wrote: > > On Tue, Sep 21, 2021 at 05:53:52PM +0200, Geert Uytterhoeven wrote: > > > On Wed, Jul 28, 2021 at 6:26 PM Laurent Pinchart wrote: > > > > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > > > > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > > > > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > > > > > Thanks for your patch! > > > > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > > > > @@ -0,0 +1,118 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder > > > > + > > > > +maintainers: > > > > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > > + > > > > +description: | > > > > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas > > > > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up > > > > + to four data lanes. > > > > + > > > > +properties: > > > > + compatible: > > > > + enum: > > > > + - renesas,r8a779a0-dsi-csi2-tx # for V3U > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + clocks: > > > > + items: > > > > + - description: Functional clock > > > > + - description: DSI (and CSI-2) functional clock > > > > + - description: PLL reference clock > > > > + > > > > + clock-names: > > > > + items: > > > > + - const: fck > > > > + - const: dsi > > > > + - const: pll > > > > > > No interrupts? > > > The hardware manual says there are 9 interrupts. > > > > Who comes up with such insanely high numbers of interrupts ? :-) > > > > What the hardware manual doesn't document is how interrupts are mapped. > > There's indeed 9 of them, and there are 9 interrupt sources, but that's > > all we know. I can easily add a > > > > interrupts: > > maxItems: 9 > > > > but I can add interrupt names without additional information. It may be > > possible to deduce some of the interrupt mappings from experiments, but > > not all of them. What do you think would be a good way forward ? Leave > > the interrupts out for now as we don't have the information ? Only list > > the interrupts but not their names ? Something else ? > > I think what we did in the past is not list the interrupts at all. > They can be added once we receive more documentation. Sounds good to me, as that's what this patch does already ;-) A R-b or A-b tag is welcome.
Hi Laurent, On Wed, Sep 22, 2021 at 10:08 AM Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Wed, Sep 22, 2021 at 08:43:57AM +0200, Geert Uytterhoeven wrote: > > On Wed, Sep 22, 2021 at 3:27 AM Laurent Pinchart wrote: > > > On Tue, Sep 21, 2021 at 05:53:52PM +0200, Geert Uytterhoeven wrote: > > > > On Wed, Jul 28, 2021 at 6:26 PM Laurent Pinchart wrote: > > > > > The R-Car MIPI DSI/CSI-2 TX is embedded in the Renesas R-Car V3U SoC. It > > > > > can operate in either DSI or CSI-2 mode, with up to four data lanes. > > > > > > > > > > Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > > > Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > > > > > > > Thanks for your patch! > > > > > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml > > > > > @@ -0,0 +1,118 @@ > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > +%YAML 1.2 > > > > > +--- > > > > > +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > > + > > > > > +title: Renesas R-Car MIPI DSI/CSI-2 Encoder > > > > > + > > > > > +maintainers: > > > > > + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > > > + > > > > > +description: | > > > > > + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas > > > > > + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up > > > > > + to four data lanes. > > > > > + > > > > > +properties: > > > > > + compatible: > > > > > + enum: > > > > > + - renesas,r8a779a0-dsi-csi2-tx # for V3U > > > > > + > > > > > + reg: > > > > > + maxItems: 1 > > > > > + > > > > > + clocks: > > > > > + items: > > > > > + - description: Functional clock > > > > > + - description: DSI (and CSI-2) functional clock > > > > > + - description: PLL reference clock > > > > > + > > > > > + clock-names: > > > > > + items: > > > > > + - const: fck > > > > > + - const: dsi > > > > > + - const: pll > > > > > > > > No interrupts? > > > > The hardware manual says there are 9 interrupts. > > > > > > Who comes up with such insanely high numbers of interrupts ? :-) > > > > > > What the hardware manual doesn't document is how interrupts are mapped. > > > There's indeed 9 of them, and there are 9 interrupt sources, but that's > > > all we know. I can easily add a > > > > > > interrupts: > > > maxItems: 9 > > > > > > but I can add interrupt names without additional information. It may be > > > possible to deduce some of the interrupt mappings from experiments, but > > > not all of them. What do you think would be a good way forward ? Leave > > > the interrupts out for now as we don't have the information ? Only list > > > the interrupts but not their names ? Something else ? > > > > I think what we did in the past is not list the interrupts at all. > > They can be added once we receive more documentation. > > Sounds good to me, as that's what this patch does already ;-) A R-b or > A-b tag is welcome. Your wish is my command... Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml new file mode 100644 index 000000000000..afeeb967393d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car MIPI DSI/CSI-2 Encoder + +maintainers: + - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> + +description: | + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up + to four data lanes. + +properties: + compatible: + enum: + - renesas,r8a779a0-dsi-csi2-tx # for V3U + + reg: + maxItems: 1 + + clocks: + items: + - description: Functional clock + - description: DSI (and CSI-2) functional clock + - description: PLL reference clock + + clock-names: + items: + - const: fck + - const: dsi + - const: pll + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Parallel input port + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: DSI/CSI-2 output port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> + #include <dt-bindings/power/r8a779a0-sysc.h> + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0xfed80000 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "fck", "dsi", "pll"; + resets = <&cpg 415>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&sn65dsi86_in>; + }; + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index b2cbb5c49358..1c9ea6279189 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6139,6 +6139,7 @@ L: dri-devel@lists.freedesktop.org L: linux-renesas-soc@vger.kernel.org S: Supported T: git git://linuxtv.org/pinchartl/media drm/du/next +F: Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml F: Documentation/devicetree/bindings/display/renesas,du.yaml