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[13/22] ARM: dts: sh73a0: Correct interrupt type for ARM TWD

Message ID a4a72b473e2897265a0fecbd5f6b5a92ea62585f.1461558315.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit a4a72b473e2897265a0fecbd5f6b5a92ea62585f
Delegated to: Simon Horman
Headers show

Commit Message

Simon Horman April 25, 2016, 4:27 a.m. UTC 
From: Geert Uytterhoeven <geert+renesas@glider.be>

The ARM TWD interrupt is a private peripheral interrupt (PPI), and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED.

For SH-Mobile AG5 devices the PPI type cannot be set, and so when we
attempt to set the type for the ARM TWD interrupt it fails.  This has
gone unnoticed because it fails silently, and because we cannot
re-configure the type it has had no impact. Nevertheless fix the type
for the TWD interrupt so that it matches the hardware configuration.

Based on patches by Jon Hunter for Tegra20/30 and OMAP4.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/sh73a0.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 639ea2d76970..c4f434cdec60 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -43,7 +43,7 @@ 
 	timer@f0000600 {
 		compatible = "arm,cortex-a9-twd-timer";
 		reg = <0xf0000600 0x20>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 		clocks = <&twd_clk>;
 	};