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[04/14] arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node

Message ID a528b4bf1a2ecb756aa65548fd5518fe82fb4648.1456445161.git.horms+renesas@verge.net.au (mailing list archive)
State Accepted
Commit a528b4bf1a2ecb756aa65548fd5518fe82fb4648
Headers show

Commit Message

Simon Horman Feb. 26, 2016, 12:07 a.m. UTC 
From: Geert Uytterhoeven <geert+renesas@glider.be>

Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 832a5665bb27..ea56066c2260 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -68,6 +68,8 @@ 
 
 	L2_CA57: cache-controller@0 {
 		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
 	};
 
 	extal_clk: extal {