| Message ID | b83b21b6477a0e31f99eaedbd36c03014b72ec8a.1707661382.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 2e45b42f1bb81921f0de7ab7de92939a293c7934 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [1/2] arm64: dts: renesas: r8a779h0: Add Ethernet-AVB support | expand |
On Sun, Feb 11, 2024 at 3:31 PM Geert Uytterhoeven <geert+renesas@glider.be> wrote: > From: Thanh Quan <thanh.quan.xn@renesas.com> > > Describe the wiring of the first Ethernet AVB instance to the Micrel > KSZ9031RNXVB PHY. > > Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > Changes compared to the BSP: > - Split in separate commits for SoC and board support, > - Apply to r8a779h0-gray-hawk-single.dts. > --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts > +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts This lacks the addition of #include <dt-bindings/gpio/gpio.h>, which is needed for the use of GPIO_* flags below. > @@ -34,6 +35,24 @@ memory@480000000 { > }; > }; > > +&avb0 { > + pinctrl-0 = <&avb0_pins>; > + pinctrl-names = "default"; > + phy-handle = <&phy0>; > + tx-internal-delay-ps = <2000>; > + status = "okay"; > + > + phy0: ethernet-phy@0 { > + compatible = "ethernet-phy-id0022.1622", > + "ethernet-phy-ieee802.3-c22"; > + rxc-skew-ps = <1500>; > + reg = <0>; > + interrupt-parent = <&gpio7>; > + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; > + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; > + }; > +}; > + Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 1bee27b2284d2eee..625e7448bc9fc1ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -15,6 +15,7 @@ / { aliases { serial0 = &hscif0; + ethernet0 = &avb0; }; chosen { @@ -34,6 +35,24 @@ memory@480000000 { }; }; +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -90,6 +109,24 @@ &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + }; + hscif0_pins: hscif0 { groups = "hscif0_data", "hscif0_ctrl"; function = "hscif0";