| Message ID | be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 0d67c0340a60829c5c1b7d09629d23bbd67696f3 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: rcar-gen3: allow changing the RPC[D2] clocks | expand |
Hi Sergei, On Fri, Sep 27, 2019 at 8:09 PM Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency > and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to > clk_register_composite() when registering the RPC[D2] clocks... > > Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Thanks for your patch! LGTM, so Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Now, before I apply this: does this make RPC-IF work? > --- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c > +++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r > > clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, > &rpc->div.hw, &clk_divider_ops, > - &rpc->gate.hw, &clk_gate_ops, 0); > + &rpc->gate.hw, &clk_gate_ops, > + CLK_SET_RATE_PARENT); > if (IS_ERR(clk)) { > kfree(rpc); > return clk; > @@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk > > clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, > &rpcd2->fixed.hw, &clk_fixed_factor_ops, > - &rpcd2->gate.hw, &clk_gate_ops, 0); > + &rpcd2->gate.hw, &clk_gate_ops, > + CLK_SET_RATE_PARENT); > if (IS_ERR(clk)) > kfree(rpcd2); Gr{oetje,eeting}s, Geert
On 10/07/2019 02:45 PM, Geert Uytterhoeven wrote: >> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency >> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to >> clk_register_composite() when registering the RPC[D2] clocks... >> >> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Thanks for your patch! > > LGTM, so > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks. :-) > Now, before I apply this: does this make RPC-IF work? Unfortunately, no. :-/ MBR, Sergei
Hi Sergei, On Mon, Oct 7, 2019 at 1:49 PM Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > On 10/07/2019 02:45 PM, Geert Uytterhoeven wrote: > >> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency > >> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to > >> clk_register_composite() when registering the RPC[D2] clocks... > >> > >> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > > Thanks for your patch! > > > > LGTM, so > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Thanks. :-) > > > Now, before I apply this: does this make RPC-IF work? > > Unfortunately, no. :-/ As per private communication, I understand the problem is elsewhere, and this patch itself is working fine, and thus safe to apply? Thanks for confirming! Gr{oetje,eeting}s, Geert
On 12/17/2019 11:43 PM, Geert Uytterhoeven wrote: [...] >>>> I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency >>>> and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to >>>> clk_register_composite() when registering the RPC[D2] clocks... >>>> >>>> Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>> >>> Thanks for your patch! >>> >>> LGTM, so >>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> >> >> Thanks. :-) >> >>> Now, before I apply this: does this make RPC-IF work? >> >> Unfortunately, no. :-/ > > As per private communication, I understand the problem is elsewhere, > and this patch itself is working fine, and thus safe to apply? Yes, I was able to lower the RPC[D2] frequencies but that didn't really help... I should mention that CLK_SET_RATE_PARENT logic seemed a bit backward to me, i.e. how the given clock know the properties of its parent clock... > Thanks for confirming! > > Gr{oetje,eeting}s, > > Geert MBR, Sergei
On Mon, Oct 7, 2019 at 1:45 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Fri, Sep 27, 2019 at 8:09 PM Sergei Shtylyov > <sergei.shtylyov@cogentembedded.com> wrote: > > I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency > > and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to > > clk_register_composite() when registering the RPC[D2] clocks... > > > > Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Thanks for your patch! > > LGTM, so > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Queueing in clk-renesas-for-v5.6. Gr{oetje,eeting}s, Geert
Index: renesas/drivers/clk/renesas/rcar-gen3-cpg.c =================================================================== --- renesas.orig/drivers/clk/renesas/rcar-gen3-cpg.c +++ renesas/drivers/clk/renesas/rcar-gen3-cpg.c @@ -464,7 +464,8 @@ static struct clk * __init cpg_rpc_clk_r clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpc->div.hw, &clk_divider_ops, - &rpc->gate.hw, &clk_gate_ops, 0); + &rpc->gate.hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); if (IS_ERR(clk)) { kfree(rpc); return clk; @@ -500,7 +501,8 @@ static struct clk * __init cpg_rpcd2_clk clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, &rpcd2->fixed.hw, &clk_fixed_factor_ops, - &rpcd2->gate.hw, &clk_gate_ops, 0); + &rpcd2->gate.hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); if (IS_ERR(clk)) kfree(rpcd2);
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to clk_register_composite() when registering the RPC[D2] clocks... Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- This patch is against the 'clk-renesas' branch of Geert Uytterhoeven's 'renesas-drivers.git' repo. drivers/clk/renesas/rcar-gen3-cpg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)