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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: arm-soc <arm@kernel.org>, soc <soc@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [GIT PULL 1/3] Renesas ARM defconfig updates for v6.7 (take two)
Date: Fri, 13 Oct 2023 14:39:13 +0200
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The following changes since commit d2efde5cc970cd21de0f94cf03e059adc1e1311b:
ARM: shmobile: defconfig: Refresh for v6.6-rc3 (2023-09-28 11:41:02 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-arm-defconfig-for-v6.7-tag2
for you to fetch changes up to 09cfdb5a97b53d117682211a4d32a39af2e819e4:
arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC (2023-10-05 14:31:10 +0200)
----------------------------------------------------------------
Renesas ARM defconfig updates for v6.7 (take two)
- Enable support for the Renesas RZ/G3S (R9A08G045) SoC in the arm64
defconfig.
----------------------------------------------------------------
Claudiu Beznea (1):
arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
The following changes since commit d2efde5cc970cd21de0f94cf03e059adc1e1311b: ARM: shmobile: defconfig: Refresh for v6.6-rc3 (2023-09-28 11:41:02 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-arm-defconfig-for-v6.7-tag2 for you to fetch changes up to 09cfdb5a97b53d117682211a4d32a39af2e819e4: arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC (2023-10-05 14:31:10 +0200) ---------------------------------------------------------------- Renesas ARM defconfig updates for v6.7 (take two) - Enable support for the Renesas RZ/G3S (R9A08G045) SoC in the arm64 defconfig. ---------------------------------------------------------------- Claudiu Beznea (1): arm64: defconfig: Enable RZ/G3S (R9A08G045) SoC arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)