From patchwork Thu Feb 25 23:53:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 8427931 Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 248CBC0553 for ; Thu, 25 Feb 2016 23:53:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 95BCD20268 for ; Thu, 25 Feb 2016 23:53:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1CEB20266 for ; Thu, 25 Feb 2016 23:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751544AbcBYXx0 (ORCPT ); Thu, 25 Feb 2016 18:53:26 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:42563 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752221AbcBYXx0 (ORCPT ); Thu, 25 Feb 2016 18:53:26 -0500 Received: from penelope.kanocho.kobe.vergenet.net (aa046235.ppp.asahi-net.or.jp [110.5.46.235]) by kirsty.vergenet.net (Postfix) with ESMTPSA id 3C96A25BE8C; Fri, 26 Feb 2016 10:53:15 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1456444395; bh=/LpdpAYQu5CcfgAvNGrlQPoNRBWAijikRxPpmkSTSf4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e4kRga+jkWgEZsARD1SrOfvk6ALbCSx+WqptzGPTG9tGqKZjfO77Nx695IkFfrN7V mMnzzEtU2QHjsMtgVTu/09uWlN70/085ARLnxgfuFyIQswUOu+QljAnKb4HhhWte/D MvM4jfvVZgsMQNLhI5qiX3mu79PJFDIsrwf2lj7Q= Received: by penelope.kanocho.kobe.vergenet.net (Postfix, from userid 7100) id 4A84C60EBF; Fri, 26 Feb 2016 10:53:10 +1100 (AEDT) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Magnus Damm , Geert Uytterhoeven , Simon Horman Subject: [PATCH 11/19] ARM: dts: r8a7790: Add L2 cache-controller nodes Date: Fri, 26 Feb 2016 08:53:00 +0900 Message-Id: X-Mailer: git-send-email 2.7.0.rc3.207.g0ac5344 In-Reply-To: References: Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Geert Uytterhoeven Add device nodes for the L2 caches, and link the CPU nodes to them. The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as 128 KiB x 16 ways). The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as 64 KiB x 8 ways). Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 24b773ae133a..ba4c2530d79f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -52,6 +52,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ + next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -67,6 +68,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu2: cpu@2 { @@ -74,6 +76,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu3: cpu@3 { @@ -81,6 +84,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + next-level-cache = <&L2_CA15>; }; cpu4: cpu@4 { @@ -88,6 +92,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu5: cpu@5 { @@ -95,6 +100,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu6: cpu@6 { @@ -102,6 +108,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; cpu7: cpu@7 { @@ -109,6 +116,7 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + next-level-cache = <&L2_CA7>; }; }; @@ -131,6 +139,18 @@ }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller@1 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;