diff mbox series

[v2,2/2] arm64: dts: renesas: r8a77980: eagle/v3msk: add QSPI flash support

Message ID fca1d012-29bf-eead-1c0d-4dd837c0bc68@cogentembedded.com (mailing list archive)
State Mainlined
Commit daa36ae015194beebdb66a94e493104a4c29ad81
Delegated to: Geert Uytterhoeven
Headers show
Series Add R8A77970 RPC-IF support | expand

Commit Message

Sergei Shtylyov June 19, 2020, 8:22 p.m. UTC 
Define the Eagle/V3MSK board dependent parts of the RPC-IF device node.
Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.

Based on the original patches by Dmitry Shifrin.

Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
 arch/arm64/boot/dts/renesas/r8a77970-eagle.dts |   67 +++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts |   67 +++++++++++++++++++++++++
 2 files changed, 134 insertions(+)

Comments

Sergei Shtylyov June 25, 2020, 9:36 a.m. UTC | #1 
Hello!

    The subject should read r8a77970, thanks Geert for noticing...
Geert Uytterhoeven July 7, 2020, 9:54 a.m. UTC | #2 
Hi Sergei,

On Fri, Jun 19, 2020 at 10:22 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the Eagle/V3MSK board dependent parts of the RPC-IF device node.
> Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.
>
> Based on the original patches by Dmitry Shifrin.
>
> Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.9, with the subject fixed.

However, one question below...

> --- renesas-devel.orig/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
> +++ renesas-devel/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
> @@ -187,12 +187,79 @@
>                 function = "i2c0";
>         };
>
> +       qspi0_pins: qspi0 {
> +               groups = "qspi0_ctrl", "qspi0_data4";
> +               function = "qspi0";
> +       };
> +
>         scif0_pins: scif0 {
>                 groups = "scif0_data";
>                 function = "scif0";
>         };
>  };
>
> +&rpc {
> +       pinctrl-0 = <&qspi0_pins>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +
> +       flash@0 {
> +               compatible = "spansion,s25fs512s", "jedec,spi-nor";
> +               reg = <0>;
> +               spi-max-frequency = <50000000>;
> +               spi-rx-bus-width = <4>;

Why no "spi-tx-bus-width = <4>;"? Same for V3MSK.
If there's no good reason to omit it, I'll add it when applying.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

Index: renesas-devel/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
===================================================================
--- renesas-devel.orig/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ renesas-devel/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -187,12 +187,79 @@ 
 		function = "i2c0";
 	};
 
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+
 	scif0_pins: scif0 {
 		groups = "scif0_data";
 		function = "scif0";
 	};
 };
 
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fs512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			bootparam@0 {
+				reg = <0x00000000 0x040000>;
+				read-only;
+			};
+			cr7@40000 {
+				reg = <0x00040000 0x080000>;
+				read-only;
+			};
+			cert_header_sa3@c0000 {
+				reg = <0x000c0000 0x080000>;
+				read-only;
+			};
+			bl2@140000 {
+				reg = <0x00140000 0x040000>;
+				read-only;
+			};
+			cert_header_sa6@180000 {
+				reg = <0x00180000 0x040000>;
+				read-only;
+			};
+			bl31@1c0000 {
+				reg = <0x001c0000 0x460000>;
+				read-only;
+			};
+			uboot@640000 {
+				reg = <0x00640000 0x0c0000>;
+				read-only;
+			};
+			uboot-env@700000 {
+				reg = <0x00700000 0x040000>;
+				read-only;
+			};
+			dtb@740000 {
+				reg = <0x00740000 0x080000>;
+			};
+			kernel@7c0000 {
+				reg = <0x007c0000 0x1400000>;
+			};
+			user@1bc0000 {
+				reg = <0x01bc0000 0x2440000>;
+			};
+		};
+	};
+};
+
 &rwdt {
 	timeout-sec = <60>;
 	status = "okay";
Index: renesas-devel/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
===================================================================
--- renesas-devel.orig/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ renesas-devel/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -212,12 +212,79 @@ 
 		power-source = <3300>;
 	};
 
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+
 	scif0_pins: scif0 {
 		groups = "scif0_data";
 		function = "scif0";
 	};
 };
 
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fs512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			bootparam@0 {
+				reg = <0x00000000 0x040000>;
+				read-only;
+			};
+			cr7@40000 {
+				reg = <0x00040000 0x080000>;
+				read-only;
+			};
+			cert_header_sa3@c0000 {
+				reg = <0x000c0000 0x080000>;
+				read-only;
+			};
+			bl2@140000 {
+				reg = <0x00140000 0x040000>;
+				read-only;
+			};
+			cert_header_sa6@180000 {
+				reg = <0x00180000 0x040000>;
+				read-only;
+			};
+			bl31@1c0000 {
+				reg = <0x001c0000 0x460000>;
+				read-only;
+			};
+			uboot@640000 {
+				reg = <0x00640000 0x0c0000>;
+				read-only;
+			};
+			uboot-env@700000 {
+				reg = <0x00700000 0x040000>;
+				read-only;
+			};
+			dtb@740000 {
+				reg = <0x00740000 0x080000>;
+			};
+			kernel@7c0000 {
+				reg = <0x007c0000 0x1400000>;
+			};
+			user@1bc0000 {
+				reg = <0x01bc0000 0x2440000>;
+			};
+		};
+	};
+};
+
 &scif0 {
 	pinctrl-0 = <&scif0_pins>;
 	pinctrl-names = "default";