[v2,0/4] Timer code cleanup.

Message

Atish Patra Dec. 13, 2018, 11:14 p.m. UTC

This patch series provides an assorted timer cleanups in RISC-V.

Changes from v1->v2:

1. Updated commit text in 1/4.
2. Added a timebase check for each cpu.
3. Added a warning for invalid hartid 4/4.

Atish Patra (3):
RISC-V: Support per-hart timebase-frequency
RISC-V: Remove per cpu clocksource
RISC-V: Fix non-smp kernel boot on SMP systems

Palmer Dabbelt (1):
dt-bindings: Correct RISC-V's timebase-frequency

Documentation/devicetree/bindings/riscv/cpus.txt |  4 +-
arch/riscv/kernel/time.c                         |  9 +----
drivers/clocksource/riscv_timer.c                | 51 +++++++++++++++++++++---
3 files changed, 49 insertions(+), 15 deletions(-)

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2.7.4