[0/2] EDAC Support for SiFive SoCs

Message ID	1553082728-9232-1-git-send-email-yash.shah@sifive.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org> From: Yash Shah <yash.shah@sifive.com> To: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com Subject: [PATCH 0/2] EDAC Support for SiFive SoCs Date: Wed, 20 Mar 2019 17:22:06 +0530 Message-Id: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> Precedence: list Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah <yash.shah@sifive.com>, robh+dt@kernel.org, bp@alien8.de, mchehab@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	EDAC Support for SiFive SoCs \| expand [0/2] EDAC Support for SiFive SoCs [1/2] edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent [2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip

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1553082728-9232-1-git-send-email-yash.shah@sifive.com (mailing list archive)

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From: Yash Shah <yash.shah@sifive.com>
To: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org,
 palmer@sifive.com, paul.walmsley@sifive.com
Subject: [PATCH 0/2] EDAC Support for SiFive SoCs
Date: Wed, 20 Mar 2019 17:22:06 +0530
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 linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com,
 Yash Shah <yash.shah@sifive.com>, robh+dt@kernel.org, bp@alien8.de,
 mchehab@kernel.org
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Series

EDAC Support for SiFive SoCs | expand

Message

Yash Shah March 20, 2019, 11:52 a.m. UTC

This patch series adds an EDAC driver and DT documentation
for FU540-C000 chip.

Initially L2 Cache controller is added as a subcomponent to this driver.

This patchset is based on Linux 5.0-rc8 and tested on HiFive Unleashed
board with additional board related patches needed for testing can be
found at dev/yashs/L2_cache_controller branch of:
https://github.com/yashshah7/riscv-linux.git

Yash Shah (2):
  edac: sifive: Add DT documentation for SiFive EDAC driver and
    subcomponent
  edac: sifive: Add EDAC driver for SiFive FU540-C000 chip

 .../devicetree/bindings/edac/sifive-edac.txt       |  40 +++
 arch/riscv/Kconfig                                 |   1 +
 drivers/edac/Kconfig                               |  13 +
 drivers/edac/Makefile                              |   1 +
 drivers/edac/sifive_edac.c                         | 297 +++++++++++++++++++++
 5 files changed, 352 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac.txt
 create mode 100644 drivers/edac/sifive_edac.c