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bh=/bJv9DuAM2pvfcOoOnP+vj4tP5tECf/i0mClvD8AEJk=; b=SRzOJ/c6Q8QNHBAuiVoQOLC3N4U1zgxKo0aMsxTv+HON+EgkAYCuc/+o7PUT14mT77 V02m8PK9ZaMWmZp4ZFH2fI2ZdmTM8MQ3X/NapAmp9NJ7k3wegxWFltLZowGTRV9ov2yl GPTsOGttHOoB9kf9tPNxU/7XR2yASTo1ChDfziUwqy0ZIQLNVCgIYbZdhKgZ/qI/AaZ9 ZvBSmmIPtQOPajtFvbC3dGpOwt8jpnonO+0+RCnxCrL775fF/q7ODpO6wiFMteMQcY3M P5tEs9bGPM6liUW23rrHH95NB6R0BVXlQ/30RYDExQID6tnYyUJI2lTsEQZScqjZJYWA CBbQ== X-Gm-Message-State: APjAAAXlEaPUokS9UM4XmtqF6st0mkQ1An+RelTpOXwS3pXZD7SPOzuF ij4R46AvVpxK0qMgw8KTyEcPgq2Nka4= X-Google-Smtp-Source: APXvYqxhNTKxGiSZcyTfaxPZffk1AyonVYUpmBTQNMKUdsKk3SjMnpPOAlRt7jZaQUZX/GU26WDQrQ== X-Received: by 2002:a63:1f61:: with SMTP id q33mr7029298pgm.325.1553082814378; Wed, 20 Mar 2019 04:53:34 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id u10sm1999435pgr.2.2019.03.20.04.53.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Mar 2019 04:53:33 -0700 (PDT) From: Yash Shah To: linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, palmer@sifive.com, paul.walmsley@sifive.com Subject: [PATCH 0/2] EDAC Support for SiFive SoCs Date: Wed, 20 Mar 2019 17:22:06 +0530 Message-Id: <1553082728-9232-1-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190320_045336_380275_D2AC7EEB X-CRM114-Status: GOOD ( 10.32 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah , robh+dt@kernel.org, bp@alien8.de, mchehab@kernel.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch series adds an EDAC driver and DT documentation for FU540-C000 chip. Initially L2 Cache controller is added as a subcomponent to this driver. This patchset is based on Linux 5.0-rc8 and tested on HiFive Unleashed board with additional board related patches needed for testing can be found at dev/yashs/L2_cache_controller branch of: https://github.com/yashshah7/riscv-linux.git Yash Shah (2): edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent edac: sifive: Add EDAC driver for SiFive FU540-C000 chip .../devicetree/bindings/edac/sifive-edac.txt | 40 +++ arch/riscv/Kconfig | 1 + drivers/edac/Kconfig | 13 + drivers/edac/Makefile | 1 + drivers/edac/sifive_edac.c | 297 +++++++++++++++++++++ 5 files changed, 352 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/sifive-edac.txt create mode 100644 drivers/edac/sifive_edac.c