Message ID | 20190312220752.128141-1-anup.patel@wdc.com (mailing list archive) |
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13 Mar 2019 06:09:48 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H8HFKkoIRvAyrM2FPAZlCvfO+U3ngTMt9osv6AUjgxw=; b=dV+j3Y1nwsXZHUB/roFywfk9B3mFPEiCbnQMnMbFjC5i76feUT5M2Go6tNoH1gepLLzuAQBUSgO8vTbzTH77GZA8jTwanxtfButSY0d1VQgABCqT3RBOzEQaaBLX+N1MDyM9Se/v4UeayJKa9OkVhOq8M7wj+8RKZXZbFWCQ1UQ= Received: from DM6PR04MB6059.namprd04.prod.outlook.com (20.178.226.89) by DM6PR04MB5643.namprd04.prod.outlook.com (20.179.48.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1709.13; Tue, 12 Mar 2019 22:08:09 +0000 Received: from DM6PR04MB6059.namprd04.prod.outlook.com ([fe80::447:8360:6df9:c934]) by DM6PR04MB6059.namprd04.prod.outlook.com ([fe80::447:8360:6df9:c934%3]) with mapi id 15.20.1686.021; Tue, 12 Mar 2019 22:08:09 +0000 From: Anup Patel <Anup.Patel@wdc.com> To: Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH 0/3] Boot RISC-V kernel from any 4KB aligned address Thread-Topic: [PATCH 0/3] Boot RISC-V kernel from any 4KB aligned address Thread-Index: AQHU2SATag7fx1KS0Uu+vlG/L6sUIQ== Date: Tue, 12 Mar 2019 22:08:09 +0000 Message-ID: <20190312220752.128141-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BY5PR13CA0028.namprd13.prod.outlook.com (2603:10b6:a03:180::41) To DM6PR04MB6059.namprd04.prod.outlook.com (2603:10b6:5:129::25) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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Boot RISC-V kernel from any 4KB aligned address
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From: Anup Patel <anup@brainfault.org> This patchset primarily extends initial page table setup using fixmap to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address. We also add 32bit defconfig to allow people to try 32bit Linux RISC-V kernel as well. The patchset is tested on SiFive Unleashed board and QEMU virt machine. It can also be found in riscv_setup_vm_v1 branch of https//github.com/avpatel/linux.git Anup Patel (3): RISC-V: Add separate defconfig for 32bit systems RISC-V: Make setup_vm() independent of GCC code model RISC-V: Allow booting kernel from any 4KB aligned address arch/riscv/configs/rv32_defconfig | 84 +++++++ arch/riscv/include/asm/fixmap.h | 5 + arch/riscv/include/asm/pgtable-64.h | 5 + arch/riscv/include/asm/pgtable.h | 6 +- arch/riscv/kernel/head.S | 2 + arch/riscv/kernel/setup.c | 4 +- arch/riscv/mm/init.c | 370 +++++++++++++++++++++++----- 7 files changed, 419 insertions(+), 57 deletions(-) create mode 100644 arch/riscv/configs/rv32_defconfig