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DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5757; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wBgsYAFQ75kzIHyXZGAJ77CniMyZP/yOG31QWscClRt2T++H4PQdVLu5GGxrSU6HetMUrI3x20CZ/wxurVLobWZU84ZDvGLsMPjvaEhbBEsA3trh+Fr6JfYXRZFV8u/8ySWHhkfbyaUnstiBlHwUGR36SOHSJVtpc+ttoJNL/oQ+gF+Ce6RdbmYfQdaBzt3vPUuxBkUyRE/Z6HshaD1WVQuxraHLg5tYC48TAHh8rekaIlar7O0k8LM186F0mUpOKfGGrdy9NRWwAZWftAVd/2b96LlwUVp4jX482eikfhqr2fA3LOngAvvP/VdhPnpp+VGmCN1CRt1SNtBnhdVNR0YewyH1fyMRHeAJ/l88YcYhQii8CZzRqhLwBQF6JL2SahKy3rhzQooAp7QYodvdMJ1KVEPFNvWnWi0h2iPzt1A= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: d5ba726e-f766-4584-de1d-08d6ade23f86 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Mar 2019 09:47:36.2683 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5757 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190321_024740_832302_7D5ABE94 X-CRM114-Status: GOOD ( 14.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , "linux-kernel@vger.kernel.org" , Mike Rapoport , Christoph Hellwig , Atish Patra , Paul Walmsley , "linux-riscv@lists.infradead.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patchset primarily extends initial page table setup using fixmap to boot Linux RISC-V kernel (64bit and 32bit) from any 4KB aligned address. We also add 32bit defconfig to allow people to try 32bit Linux RISC-V kernel as well. The patchset is based on Linux-5.1-rc1 and tested on SiFive Unleashed board and QEMU virt machine. It can also be found in riscv_setup_vm_v2 branch of https//github.com/avpatel/linux.git Changes since v1: - Add kconfig option BOOT_PAGE_ALIGNED to enable 4KB aligned booting - Improved initial page table setup code to select best/biggest possible mapping size based on load address alignment - Added PATCH4 to remove redundant trampoline page table - Added PATCH5 to fix memory reservation in setup_bootmem() Anup Patel (5): RISC-V: Add separate defconfig for 32bit systems RISC-V: Make setup_vm() independent of GCC code model RISC-V: Allow booting kernel from any 4KB aligned address RISC-V: Remove redundant trampoline page table RISC-V: Fix memory reservation in setup_bootmem() arch/riscv/Kconfig | 11 + arch/riscv/configs/rv32_defconfig | 84 ++++++ arch/riscv/include/asm/fixmap.h | 5 + arch/riscv/include/asm/pgtable-64.h | 5 + arch/riscv/include/asm/pgtable.h | 6 +- arch/riscv/kernel/head.S | 15 +- arch/riscv/kernel/setup.c | 4 +- arch/riscv/mm/init.c | 391 +++++++++++++++++++++++----- 8 files changed, 450 insertions(+), 71 deletions(-) create mode 100644 arch/riscv/configs/rv32_defconfig