[0/5] arch: riscv: add board and SoC DT file support

Message ID	20190602080126.31075-1-paul.walmsley@sifive.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org> From: Paul Walmsley <paul.walmsley@sifive.com> To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 0/5] arch: riscv: add board and SoC DT file support Date: Sun, 2 Jun 2019 01:01:21 -0700 Message-Id: <20190602080126.31075-1-paul.walmsley@sifive.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	arch: riscv: add board and SoC DT file support \| expand [0/5] arch: riscv: add board and SoC DT file support [1/5] arch: riscv: add support for building DTB files from DT source data [2/5] dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 [3/5] dt-bindings: riscv: convert cpu binding to json-schema [4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC [5/5] riscv: dts: add initial board data for the SiFive HiFive Unleashed

Message ID

20190602080126.31075-1-paul.walmsley@sifive.com (mailing list archive)

Headers

From: Paul Walmsley <paul.walmsley@sifive.com>
To: linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: [PATCH 0/5] arch: riscv: add board and SoC DT file support
Date: Sun,  2 Jun 2019 01:01:21 -0700
Message-Id: <20190602080126.31075-1-paul.walmsley@sifive.com>
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Series

arch: riscv: add board and SoC DT file support | expand

Message

Paul Walmsley June 2, 2019, 8:01 a.m. UTC

Add support for building flattened DT files from DT source files under
arch/riscv/boot/dts.  Follow existing kernel precedent from other SoC
architectures.  Start our board support by adding initial support for
the SiFive FU540 SoC and the first development board that uses it, the
SiFive HiFive Unleashed A00.

This third version of the patch set adds I2C data for the chip,
incorporates all remaining changes that riscv-pk was making
automatically, and addresses a comment from Rob Herring
<robh@kernel.org>.

Boot-tested on v5.2-rc1 on a HiFive Unleashed A00 board, using the
BBL and open-source FSBL, with modifications to pass in the DTB
file generated by these patches.

This patch series can be found, along with the PRCI patch set
and the DT macro prerequisite patch, at:

https://github.com/sifive/riscv-linux/tree/dev/paulw/dts-v5.2-rc1


- Paul


Paul Walmsley (5):
  arch: riscv: add support for building DTB files from DT source data
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive
    FU540
  dt-bindings: riscv: convert cpu binding to json-schema
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  riscv: dts: add initial board data for the SiFive HiFive Unleashed

 .../devicetree/bindings/riscv/cpus.yaml       | 168 ++++++++++++++
 .../devicetree/bindings/riscv/sifive.yaml     |  25 ++
 MAINTAINERS                                   |   9 +
 arch/riscv/boot/dts/Makefile                  |   2 +
 arch/riscv/boot/dts/sifive/Makefile           |   2 +
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 215 ++++++++++++++++++
 .../boot/dts/sifive/hifive-unleashed-a00.dts  |  67 ++++++
 7 files changed, 488 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
 create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
 create mode 100644 arch/riscv/boot/dts/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/Makefile
 create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
 create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts