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Mon, 9 Mar 2020 11:02:42 +0000 From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Thomas Gleixner , Jason Cooper , Marc Zyngier Subject: [PATCH v4 0/5] New RISC-V Local Interrupt Controller Driver Date: Mon, 9 Mar 2020 16:32:06 +0530 Message-Id: <20200309110211.91130-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: MAXPR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::13) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (106.51.22.61) by MAXPR01CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:49::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.11 via Frontend Transport; Mon, 9 Mar 2020 11:02:36 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [106.51.22.61] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 139dcd0a-ac2f-4989-d3e7-08d7c419638e X-MS-TrafficTypeDiagnostic: MN2PR04MB5517: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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The overall approach is inspired from the way per-CPU local interrupts are handled by Linux ARM64 and ARM GICv3 driver. Few advantages of this new driver over previous one are: 1. It registers all local interrupts as per-CPU interrupts 2. The KVM RISC-V can use this driver to implement interrupt handler for per-HART guest external interrupt defined by the RISC-V H-Extension 3. In future, we can develop drivers for devices with per-HART interrupts without changing arch code or this driver With this patchset, output of "cat /proc/interrupts" looks as follows: CPU0 CPU1 CPU2 CPU3 2: 379 0 0 0 SiFive PLIC 10 ttyS0 3: 591 0 0 0 SiFive PLIC 8 virtio0 5: 5079 10821 8435 12984 RISC-V INTC 5 riscv-timer IPI0: 2045 2537 891 870 Rescheduling interrupts IPI1: 9 269 91 168 Function call interrupts IPI2: 0 0 0 0 CPU stop interrupts The patchset is based up Linux-5.6-rc5 and can be found at riscv_intc_v4 branch of: https://github.com/avpatel/linux.git Changes since v3: - Rebased to Linux-5.6-rc5 and Atish's PLIC patches - Added separate patch to rename and move plic_find_hart_id() to arch directory - Use riscv_of_parent_hartid() in riscv_intc_init() instead of atomic counter Changes since v2: - Dropped PATCH2 since it was merged long-time back - Rebased series from Linux-4.19-rc2 to Linux-5.6-rc2 Changes since v1: - Removed changes related to puggable IPI triggering - Separate patch for self-contained IPI handling routine - Removed patch for GENERIC_IRQ kconfig options - Added patch to remove do_IRQ() function - Rebased upon Atish's SMP patches Anup Patel (5): RISC-V: self-contained IPI handling routine RISC-V: Rename and move plic_find_hart_id() to arch directory irqchip: RISC-V Per-HART Local Interrupt Controller Driver clocksource: timer-riscv: Make timer interrupt as a per-CPU interrupt RISC-V: Remove do_IRQ() function arch/riscv/Kconfig | 1 + arch/riscv/include/asm/irq.h | 5 -- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/smp.h | 3 + arch/riscv/kernel/cpu.c | 16 ++++ arch/riscv/kernel/entry.S | 4 +- arch/riscv/kernel/irq.c | 33 +------ arch/riscv/kernel/smp.c | 11 ++- arch/riscv/kernel/traps.c | 2 - drivers/clocksource/timer-riscv.c | 79 +++++++++++------ drivers/irqchip/Kconfig | 13 +++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-riscv-intc.c | 134 +++++++++++++++++++++++++++++ drivers/irqchip/irq-sifive-plic.c | 40 ++++----- include/linux/cpuhotplug.h | 1 + 15 files changed, 256 insertions(+), 88 deletions(-) create mode 100644 drivers/irqchip/irq-riscv-intc.c