| Message ID | 20200518091441.94843-1-anup.patel@wdc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | More improvements for multiple PLICs | expand |
On Mon, 18 May 2020 02:14:38 PDT (-0700), Anup Patel wrote: > This series does more improvements for supporting multiple PLIC > instances. > > PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish > multiple PLIC instances in boot prints. > > These patches are based up Linux-5.7-rc5 and can be found at > plic_imp_v2 branch at: https://github.com/avpatel/linux.git > > To try this patches, we will need: > 1. OpenSBI multi-PLIC and multi-CLINT support which can be found in > multi_plic_clint_v1 branch at: > https://github.com/avpatel/opensbi.git > 2. QEMU RISC-V multi-socket support which can be found in > riscv_multi_socket_v1 branch at: > https://github.com/avpatel/qemu.git > > Changes since v1: > - Re-arranged PATCHs to have fixes first > - Added Fixes tag to PATCH1 and PATCH2 > - Use %pOFP in boot print to distinguish PLIC instance > > Anup Patel (3): > irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() > irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is > present > irqchip/sifive-plic: Improve boot prints for multiple PLIC instances > > drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) Thanks! Aside from that parallelism question this LGTM. IIRC Marc picked up the last round, so I'm assuming this would go in through his tree as well.
On Mon, 18 May 2020 14:44:38 +0530, Anup Patel wrote: > This series does more improvements for supporting multiple PLIC > instances. > > PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish > multiple PLIC instances in boot prints. > > These patches are based up Linux-5.7-rc5 and can be found at > plic_imp_v2 branch at: https://github.com/avpatel/linux.git > > [...] Applied to irq/irqchip-next, thanks! [1/3] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() commit: 2458ed31e9b9ab40d78a452ab2650a0857556e85 [2/3] irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present commit: 2234ae846ccb9ebdf4c391824cb79e73674dceda [3/3] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances commit: 0e375f51017bcc86c23979118b10445c424ef5ad Cheers, M.
This series does more improvements for supporting multiple PLIC instances. PATCH1 and PATCH2 are fixes whereas PATCH3 helps users distinguish multiple PLIC instances in boot prints. These patches are based up Linux-5.7-rc5 and can be found at plic_imp_v2 branch at: https://github.com/avpatel/linux.git To try this patches, we will need: 1. OpenSBI multi-PLIC and multi-CLINT support which can be found in multi_plic_clint_v1 branch at: https://github.com/avpatel/opensbi.git 2. QEMU RISC-V multi-socket support which can be found in riscv_multi_socket_v1 branch at: https://github.com/avpatel/qemu.git Changes since v1: - Re-arranged PATCHs to have fixes first - Added Fixes tag to PATCH1 and PATCH2 - Use %pOFP in boot print to distinguish PLIC instance Anup Patel (3): irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() irqchip/sifive-plic: Setup cpuhp once after boot CPU handler is present irqchip/sifive-plic: Improve boot prints for multiple PLIC instances drivers/irqchip/irq-sifive-plic.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)