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d="scan'208";a="38426616" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:32:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:32:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:32:47 -0700 From: To: , , , , , , , Subject: [PATCH v3 0/5] Add support for the PolarFire SoC system controller Date: Wed, 23 Dec 2020 16:32:47 +0000 Message-ID: <20201223163247.28923-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201223_113254_085814_8212DCA8 X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, j.neuschaefer@gmx.net, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley This patch series adds support for the system controller on the PolarFire SoC, using the mailbox framework. A Microchip directory in the SoC subsystem has been created to hold the mailbox client driver and will be used for future service drivers. This directory is included by the kconfig option: CONFIG_SOC_MICROCHIP_POLARFIRE, so this patch series depends on Atish Patra's PolarFire SoC support patches which introduce that option. It further depends on the MAINTAINERS entry created in the same series. Changes from v2: * Further reworked dt bindings to satisfy errors and feedback (hopefully phandle array is the correct type for the mboxes) * Full maintainers entry moved to Atish's PFSoC support series, this series now only adds mailbox driver * Converted config options from MPFS to POLARFIRE_SOC so they are more recognisable * Further simplified driver code from feedback Changes from v1: * Squashed header into first patch * Fixed DT binding warnings & small fixes * Cleaned up drivers from feedback Conor Dooley (5): mbox: add polarfire soc system controller mailbox dt-bindings: add bindings for polarfire soc mailbox soc: add polarfire soc system controller dt-bindings: add bindings for polarfire soc system controller MAINTAINERS: add maintainers for polarfire soc mailbox driver .../mailbox/microchip,mailbox-mpfs.yaml | 47 +++ .../microchip,mpfs_sys_controller.yaml | 34 +++ MAINTAINERS | 1 + drivers/mailbox/Kconfig | 12 + drivers/mailbox/Makefile | 2 + drivers/mailbox/mailbox-mpfs.c | 285 ++++++++++++++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/microchip/Kconfig | 10 + drivers/soc/microchip/Makefile | 1 + drivers/soc/microchip/mpfs-sys-controller.c | 127 ++++++++ include/soc/microchip/mpfs.h | 51 ++++ 12 files changed, 572 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs_sys_controller.yaml create mode 100644 drivers/mailbox/mailbox-mpfs.c create mode 100644 drivers/soc/microchip/Kconfig create mode 100644 drivers/soc/microchip/Makefile create mode 100644 drivers/soc/microchip/mpfs-sys-controller.c create mode 100644 include/soc/microchip/mpfs.h