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[v1,0/3] More PolarFire SoC Fixes for 5.18

Message ID 20220408133543.3537118-1-conor.dooley@microchip.com (mailing list archive)
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Series More PolarFire SoC Fixes for 5.18 | expand

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Conor Dooley April 8, 2022, 1:35 p.m. UTC 
Hey,
After the clock driver for the PolarFire SoC was accepted I started work
on the onboard RTC & found out that the reference clock for the rtc was
actually missing from the clock driver.

While restructuring the clock driver to add support for the rtc
reference, I noticed that there were some problems with how the FIC
clocks were being used. The FIC clocks are the cpu side inputs to the
AXI fabric interconnections & are not the clocks for any peripherals.

This series fixes the problems I noticed:
- the fic clocks incorrectly had the AHB clock as their parents
- the last fic, named differently to the others, had not been set as
  a critical clock
- some peripherals on the fabric side were incorrectly using the cpu
  side fic clocks, resulting in incorrect rates.

I added fixes tags to these patches in the hope that they will make it
into 5.18. I kept series separate from [0] as that fixes something that
is broken, while these are only wrong.

Thanks,
Conor.

[0] https://lore.kernel.org/linux-riscv/20220408131352.3421559-1-conor.dooley@microchip.com/T/#u

Conor Dooley (3):
  clk: microchip: mpfs: fix parents for FIC clocks
  clk: microchip: mpfs: mark CLK_ATHENA as critical
  riscv: dts: microchip: fix usage of fic clocks on mpfs

 .../dts/microchip/microchip-mpfs-fabric.dtsi     | 16 ++++++++++++++--
 .../riscv/boot/dts/microchip/microchip-mpfs.dtsi |  2 +-
 drivers/clk/microchip/clk-mpfs.c                 | 16 +++++++++-------
 3 files changed, 24 insertions(+), 10 deletions(-)