[0/3] perf: RISC-V: fix access to the highest available counter

Message

Sergey Matyukevich June 23, 2022, 11:27 a.m. UTC

Hi all,

This patch series suggests some fixes and improvements for the bookkeeping
of the PMU counter indexes. The first patch fixes pmu_ctr_list array size
to prevent memory access beyond the allocated array. The second patch
fixes access to the highest available PMU counter.

The accompanying OpenSBI fix is available for review here:
- https://github.com/riscv-software-src/opensbi/pull/260

Note that if custom SBI firmware does not support firmware events, then
current driver behavior makes inaccessible the hardware counter with
the highest index.

Finally, the third patch attempts to provide support for any gaps in PMU
counter indexes. For this purpose pmu_ctr_list array is replaced by IDR.

Regards,
Sergey

Sergey Matyukevich (3):
  perf: RISC-V: fix access beyond allocated array
  perf: RISC-V: allow to use the highest available counter
  perf: RISC-V: support noncontiguous pmu counter IDs

 drivers/perf/riscv_pmu_legacy.c |  4 +-
 drivers/perf/riscv_pmu_sbi.c    | 88 +++++++++++++++++++++++----------
 include/linux/perf/riscv_pmu.h  |  2 +-
 3 files changed, 65 insertions(+), 29 deletions(-)