From patchwork Tue Jun 28 11:45:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nikita Shubin X-Patchwork-Id: 12898140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6E03C43334 for ; Tue, 28 Jun 2022 11:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=uTWEw2hY/QDzg1TX3bcy30vAQfMIQbfT4IcYBkOca9M=; b=l+Z9JaNwx5ohHw 161dHWZpvddDvVk+jj4ODv8kW0PotRVW68ykTibRUvNC8Iz51COzzgr7G+1wSB0Akb9R2IYAhzTik blDtGW3BAdUxJU2nb13sx8dap1Thn2/mmFXbc1d+sXR4eBVJxVYeSraTKgblfI7cAn2RH7NfdSpJd AUzd5l42CjwdMtaIxuuxDWVHi/31Ezlx0u6hdf/9RNkMCvcspbnPmM7msn0hS2UoDLsAaCkNNpUUK kLyT1xZrxiyiU7MiDwNmSYbBcDLM0ecU7IdmrVzoOhPDP3w0wb3Fl0DiS62vKnl1K9LkAH2vxS+Ju +99FY1DQB3+uBw8sn/CA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o69gJ-005zhm-Ej; Tue, 28 Jun 2022 11:46:59 +0000 Received: from forward105p.mail.yandex.net ([77.88.28.108]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o69g4-005zc0-Sk; Tue, 28 Jun 2022 11:46:48 +0000 Received: from forward100q.mail.yandex.net (forward100q.mail.yandex.net [IPv6:2a02:6b8:c0e:4b:0:640:4012:bb97]) by forward105p.mail.yandex.net (Yandex) with ESMTP id 10FC62FD96EB; Tue, 28 Jun 2022 14:46:35 +0300 (MSK) Received: from vla1-af84b0e8a1e8.qloud-c.yandex.net (vla1-af84b0e8a1e8.qloud-c.yandex.net [IPv6:2a02:6b8:c0d:991:0:640:af84:b0e8]) by forward100q.mail.yandex.net (Yandex) with ESMTP id 0B7C56F40B16; Tue, 28 Jun 2022 14:46:35 +0300 (MSK) Received: from vla3-178a3f795968.qloud-c.yandex.net (vla3-178a3f795968.qloud-c.yandex.net [2a02:6b8:c15:2584:0:640:178a:3f79]) by vla1-af84b0e8a1e8.qloud-c.yandex.net (mxback/Yandex) with ESMTP id TR9ypVqcip-kXfqs477; Tue, 28 Jun 2022 14:46:35 +0300 X-Yandex-Fwd: 2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1656416795; bh=KmAhe3GOyQCf3f/h40/f2dj9cqeEBZpz3rTHjKTlv1g=; h=Date:Subject:Cc:To:From:Message-Id; b=ie+vRnDuLEVcB3Leq2RJql7tFz8orUklnEO1RQQVkpZgB1NvgMxDqT8OOjwuzlJ7V vEHfzMwgts0oBX26/NmR5WkPi90VbAXLOE3cDq3XRr2mVO3nAAXYSF04cCYtkcRkRM Qio3zqOQ9qOYPvsfCeuVykXpMqwb+x87Rc5jY+CU= Authentication-Results: vla1-af84b0e8a1e8.qloud-c.yandex.net; dkim=pass header.i=@maquefel.me Received: by vla3-178a3f795968.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id s5dKAuvn1y-kVMCLslW; Tue, 28 Jun 2022 14:46:32 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) From: Nikita Shubin To: Cc: linux@yadro.com, Genevieve Chan , =?utf-8?b?Sm/Do28gTcOhcmlvIERvbWluZ29z?= , Nikita Shubin , Alexander Shishkin , Anup Patel , Jiri Olsa , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Namhyung Kim Subject: [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU Date: Tue, 28 Jun 2022 14:45:54 +0300 Message-Id: <20220628114625.166665-1-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_044646_070158_7897791C X-CRM114-Status: GOOD ( 10.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Nikita Shubin From: Nikita Shubin This series aims to provide matching vendor SoC with corresponded JSON bindings. The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example for Sifive Unmatched the corresponding string will be: 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core Where MIMPID can vary as all impl supported the same number of events, this might not be true for all future SoC however. Also added SBI firmware events pretty names, as any firmware that supports SBI PMU should also support firmare events [1]. Series depends on patch by Anup Patel, exposing mvendor, marchid and mimpid to "/proc/cpuinfo" [2]. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://lkml.org/lkml/2022/6/20/498 Link to previous version: https://patchwork.kernel.org/project/linux-riscv/list/?series=653649 See original cover letter by João Mário Domingos: https://patchwork.kernel.org/project/linux-riscv/cover/20211116154812.17008-1-joao.mario@tecnico.ulisboa.pt/ Tested with the following OpenSBI device tree bindings: ``` pmu { compatible = "riscv,pmu"; riscv,event-to-mhpmcounters = <0x03 0x06 0x18 0x10001 0x10002 0x18 0x10009 0x10009 0x18 0x10011 0x10011 0x18 0x10019 0x10019 0x18 0x10021 0x10021 0x18>; riscv,event-to-mhpmevent = <0x03 0x00000000 0x1801 0x04 0x00000000 0x0302 0x05 0x00000000 0x4000 0x06 0x00000000 0x6001 0x10001 0x00000000 0x0202 0x10002 0x00000000 0x0402 0x10009 0x00000000 0x0102 0x10011 0x00000000 0x2002 0x10019 0x00000000 0x1002 0x10021 0x00000000 0x0802>; riscv,raw-event-to-mhpmcounters = <0x00000000 0x03ffff00 0x0 0x0 0x18 0x00000000 0x0007ff01 0x0 0x1 0x18 0x00000000 0x00003f02 0x0 0x2 0x18>; }; ``` --- v4->v5: Atish Patra: - dropped cycle, time instret std arch events - format config is now 48-bit wide Arnaldo Carvalho de Melo: - fixed cpuid leakage - no "if" before free Will Deacon: - simply use "config:63" --- Nikita Shubin (4): drivers/perf: riscv_pmu_sbi: perf format perf tools riscv: Add support for get_cpuid_str function perf arch events: riscv sbi firmware std event files perf vendor events riscv: add Sifive U74 JSON file drivers/perf/riscv_pmu_sbi.c | 20 +++ tools/perf/arch/riscv/util/Build | 1 + tools/perf/arch/riscv/util/header.c | 106 ++++++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 17 +++ .../arch/riscv/riscv-sbi-firmware.json | 134 ++++++++++++++++++ .../arch/riscv/sifive/u74/firmware.json | 68 +++++++++ .../arch/riscv/sifive/u74/instructions.json | 92 ++++++++++++ .../arch/riscv/sifive/u74/memory.json | 32 +++++ .../arch/riscv/sifive/u74/microarch.json | 57 ++++++++ 9 files changed, 527 insertions(+) create mode 100644 tools/perf/arch/riscv/util/header.c create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json