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([51.37.234.167]) by smtp.gmail.com with ESMTPSA id j9-20020a05600c410900b003a02cbf862esm7330892wmi.13.2022.07.11.11.44.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Jul 2022 11:44:07 -0700 (PDT) From: Conor Dooley To: Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/2] Add the JH7100's Monitor Core Date: Mon, 11 Jul 2022 19:43:24 +0100 Message-Id: <20220711184325.1367393-1-mail@conchuod.ie> X-Mailer: git-send-email 2.37.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220711_114411_604001_511F9FE5 X-CRM114-Status: UNSURE ( 8.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Hey Emil, Following on from my RFC [0], here's the real patches adding the monitor core for the JH7100 w/ the ordering changed as requested. I had a look in the SiFive E24 docs [1] & in [2] which said "16KB I-cache with 32 Byte cache line". Didn't have anything else to go on, so I kept the same ratio between lines/sets/size as other SiFive monitor cores, but since they're not 32 bit I dunno if that's correct (IOW it is a wild guess). The dts patch depends on adding the series adding the cpu-map [3]: Thanks, Conor. 0: https://lore.kernel.org/linux-riscv/20220710111330.3920699-1-mail@conchuod.ie/ 1: https://sifive.cdn.prismic.io/sifive/dc408861-94ce-4d82-a704-caddec98609d_e24_core_complex_manual_21G3.pdf 2: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf 3: https://lore.kernel.org/linux-riscv/20220705190435.1790466-1-mail@conchuod.ie/ Conor Dooley (2): dt-bindings: riscv: document the sifive e24 riscv: dts: starfive: add the missing monitor core .../devicetree/bindings/riscv/cpus.yaml | 2 ++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+) base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 prerequisite-patch-id: 946df827e9dad8ca6e9751fe4ba01fd5fe9d18cc prerequisite-patch-id: 59626290ee7b1e725bd446a4b7170ee2d6ca9bc0 prerequisite-patch-id: e57a94cb7d69855a4e2d6044dcf86fbfe35cb696 prerequisite-patch-id: 0ba94fd09377953ec4e9692358de569a7932bfa3 prerequisite-patch-id: 398e9b178ce51c924bbd9115020d84b677f773bb