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([171.76.87.63]) by smtp.gmail.com with ESMTPSA id o8-20020a170902d4c800b0016be9fa6807sm13486685plg.284.2022.07.27.04.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jul 2022 04:43:52 -0700 (PDT) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v2 0/2] Improve CLOCK_EVT_FEAT_C3STOP feature setting Date: Wed, 27 Jul 2022 17:13:00 +0530 Message-Id: <20220727114302.302201-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_044354_840235_BFC5CD09 X-CRM114-Status: UNSURE ( 7.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series improves the RISC-V timer driver to set CLOCK_EVT_FEAT_C3STOP feature based on RISC-V platform capabilities. These patches can also be found in riscv_timer_dt_imp_v2 branch at: https://github.com/avpatel/linux.git Changes since v1: - Rebased on Linux-5.19-rc8 - Renamed "riscv,always-on" DT property to "riscv,timer-can-wake-cpu" Anup Patel (2): dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ drivers/clocksource/timer-riscv.c | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-)