From patchwork Fri Aug 19 08:57:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12948570 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4959C25B0E for ; Fri, 19 Aug 2022 08:58:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=nIq8HnCcg4AsCWjhta2qVoMn/U36d6BE+iv2J0koSYc=; b=fJuA0IAYjyV+qu oIX70VRwsXKbe/obqQFTiw2TGH/ErdKGHmn3REkvB4Xq+kkJKFbOzMysR1YC9Bs/cd8ZuYWXEnPGp iNeWM9+oY5+Fgm9Q6EZgIXCWkLNCx83a6xEwWdmNmA4wC3FTTslvJaVR/tCAT+5ENO+RA49kyJn6c gfS1mkkaeURoVynTR8v9NLHz3S6s1XjOp7j1uCkQuEXQdCBHnUxFV+4iPXSrmThOwT28+U7VwBbXs jJ0M2eMn3pnivKhkBxA+AJunSDEjqnL1vgGisZ/m+C1GBh+NmojvJj/cTPMFV6+wdoX0VoyPYiRlN 8miVYWNr4sm0HrRb44kg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOxpT-004Rbq-5R; Fri, 19 Aug 2022 08:58:11 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oOxpP-004Rad-Sx for linux-riscv@lists.infradead.org; Fri, 19 Aug 2022 08:58:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660899487; x=1692435487; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=PzACd/Gw+wpI2DNzrz4m8wTQM9ww418kezYNPDtbSrE=; b=gp0Rp/PjpylQXYLQsbXhUIvBr00Fn38gQif3ueCD5ThvBm5sZLd/2oZ+ dd8lkmjzfu2NQwR7tC265FTATcrlwbHpkN2ENLMpc0i93HaX12AILJUeU 126FblG7MPjmF4j58z7h2jFvf7fh3bj31L9k2ZIe2H8Dt7gC6xwBwiWK0 JG2BfQ3W92IaJ2MYMbr31abKeljs7kOBzOb/i0U7W4pFjCte4/NvXn3iW TccvLMieYehWXob9US1Lfa7kDhTZPjCdhQMr+B6Mnykk36E8haUQs+LKa jxhiNb9s9YH8esDmI0xoJT4ENSZ2F/KC1v41WdMN5LteNrKJduooNbyFM A==; X-IronPort-AV: E=Sophos;i="5.93,247,1654585200"; d="scan'208";a="170004562" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Aug 2022 01:58:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 19 Aug 2022 01:58:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 19 Aug 2022 01:58:04 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Rob Herring" , Krzysztof Kozlowski CC: Daire McNamara , , , , , Conor Dooley Subject: [PATCH v9 0/4] Microchip soft ip corePWM driver Date: Fri, 19 Aug 2022 09:57:00 +0100 Message-ID: <20220819085703.4161266-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_015808_047235_624624DA X-CRM114-Status: GOOD ( 16.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey Uwe, all, 6.0-rc1 has rolled around so here is the promised ~v8~v9. The pre 6.0-rc1 cover letter/series is here: https://lore.kernel.org/linux-pwm/20220721172109.941900-1-mail@conchuod.ie I'll take the dts change myself once the rest is merged. There is one change here that is not directly from your feedback on v7, Iadded a test for invalid PERIOD_STEPS values, in which case we abort if the period is locked and cannot be fixed. Hopefully the rounding is not ruined.. Thanks, Conor. Changes since v8: - fixed a(nother) raw 64 bit division (& built it for riscv32!) - added a check to make sure we don't try to sleep for 0 us Changes since v7: - rebased on 6.0-rc1 - reworded comments you highlighted in v7 - fixed the overkill sleeping - removed the unused variables in calc_duty - added some extra comments to explain behaviours you questioned in v7 - make the mutexes un-interruptible - fixed added the 1s you suggested for the if(period_locked) logic - added setup of the channel_enabled shadowing - fixed the period reporting for the negedge == posedge case in get_state() I had to add the enabled check, as otherwise it broke setting the period for the first time out of reset. - added a test for invalid PERIOD_STEPS values, in which case we abort if we cannot fix the period Changes from v6: - Dropped an unused variable that I'd missed - Actually check the return values of the mutex lock()s - Re-rebased on -next for the MAINTAINERS patch (again...) Changes from v5: - switched to a mutex b/c we must sleep with the lock taken - simplified the locking in apply() and added locking to get_state() - reworked apply() as requested - removed the loop in the period calculation (thanks Uwe!) - add a copy of the enable registers in the driver to save on reads. - remove the second (useless) write to sync_update - added some missing rounding in get_state() - couple other minor cleanups as requested in: https://lore.kernel.org/linux-riscv/20220709160206.cw5luo7kxdshoiua@pengutronix.de/ Changes from v4: - dropped some accidentally added files Conor Dooley (4): dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: fix the icicle's #pwm-cells pwm: add microchip soft ip corePWM driver MAINTAINERS: add pwm to PolarFire SoC entry .../bindings/pwm/microchip,corepwm.yaml | 4 +- MAINTAINERS | 1 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-microchip-core.c | 400 ++++++++++++++++++ 6 files changed, 416 insertions(+), 2 deletions(-) create mode 100644 drivers/pwm/pwm-microchip-core.c base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868