| Message ID | 20220825180417.1259360-1-mail@conchuod.ie (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add a PolarFire SoC l2 compatible | expand |
From: Conor Dooley <conor.dooley@microchip.com> On Thu, 25 Aug 2022 19:04:16 +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Whilst re-running checks before sending my dt-fixes PR today I noticed > that I had introduced another dtbs_check warning by applying one of the > patches in it. > > PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts > re-uses the compatible of currently) which only has 3. Add a new string > to the binding like should've been done in the first place... > > [...] @Palmer, I have applied these to my dt-fixes, branch as the commit they fix is there too. As I mentioned on IRC, patches for this dt-binding are usually merged via the riscv tree so I have taken the liberty of bundling it with the dts change. You may get this in a PR friday morning, but more likely early next week. Conor. [1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible https://git.kernel.org/conor/c/17e4732d1d8a [2/2] riscv: dts: microchip: use an mpfs specific l2 compatible https://git.kernel.org/conor/c/0dec364ffeb6 Thanks, Conor.
From: Conor Dooley <conor.dooley@microchip.com> Whilst re-running checks before sending my dt-fixes PR today I noticed that I had introduced another dtbs_check warning by applying one of the patches in it. PolarFire SoC has 4 cache interrupts, unlike the fu540 (which the dts re-uses the compatible of currently) which only has 3. Add a new string to the binding like should've been done in the first place... The driver does not care which compatible it matches against, and just uses as many interrupts as are in the dts so will happily work away without any needed changes there. @Palmer, you can take this directly as long as my fixes PR for rc3 is merged if you like, since the application path for the binding is via you anyway. I suppose I could take both too, but whatever works best for you (: Thanks, Conor. Conor Dooley (2): dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible riscv: dts: microchip: use an mpfs specific l2 compatible .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++------- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 2 files changed, 50 insertions(+), 31 deletions(-)