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([171.76.81.110]) by smtp.gmail.com with ESMTPSA id a6-20020a170902ecc600b0016ed5266a5csm7517607plh.170.2022.08.29.05.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 05:52:49 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH 0/4] Add PMEM support for RISC-V Date: Mon, 29 Aug 2022 18:22:22 +0530 Message-Id: <20220829125226.511564-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220829_055252_433004_58644FB7 X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Linux NVDIMM PEM drivers require arch support to map and access the persistent memory device. This series adds RISC-V PMEM support using recently added Svpbmt and Zicbom support. These patches can also be found in riscv_pmem_v1 branch at: https://github.com/avpatel/linux.git Anup Patel (4): RISC-V: Fix ioremap_cache() and ioremap_wc() for systems with Svpbmt RISC-V: Move riscv_init_cbom_blocksize() to cacheflush.c RISC-V: Implement arch specific PMEM APIs RISC-V: Enable PMEM drivers arch/riscv/Kconfig | 1 + arch/riscv/configs/defconfig | 1 + arch/riscv/include/asm/cacheflush.h | 2 ++ arch/riscv/include/asm/io.h | 10 ++++++++ arch/riscv/include/asm/pgtable.h | 2 ++ arch/riscv/mm/Makefile | 1 + arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 36 ---------------------------- arch/riscv/mm/pmem.c | 21 ++++++++++++++++ 9 files changed, 75 insertions(+), 36 deletions(-) create mode 100644 arch/riscv/mm/pmem.c