From patchwork Tue Aug 30 10:17:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12959042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E851ECAAD4 for ; Tue, 30 Aug 2022 10:20:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=LkRT7vvF+PLaSzPGrZNBW0bMEFNWnnCiD3mA+Ra4ioQ=; b=eoQI1pfmGe1s1E PHYJlSgndaDygmCQpG3ppH3Gf2BGBPZplB7UJVZvVwNhZE5LXjBTusvetVGVTjlM+IpVkslAcWV5O j6RSW1thCAmR6gzad1LHrANRvYy108+lg2bJ9PmlwS02wTrjPTnaC1ZB0o8I7fiKowIjZ8kWu7R5K kzTLMVScoyuR9B/oPOu2+VRClV3Rc+/O/5kOE2LR2LLNmX+ga+FYklF+WA8JjsQfqo6BBheBdHyE2 APdJETPCvkqR+ciI3L1aTE87oFoSWTYhgvzRBX1msZFDhw4/ESKnU5yhvlXusa6GyG/noOo5L5h59 mo9Mz4v/yYZ4cdmrqbkA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSyM5-00G72d-Ra; Tue, 30 Aug 2022 10:20:25 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oSyKK-00G69b-4o for linux-riscv@lists.infradead.org; Tue, 30 Aug 2022 10:18:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854716; x=1693390716; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=G5DqqeYFftRy6E94k8NanMKhorLf/PE/ar2pCiXSZaQ=; b=reJB9oYpknL8qkRPXwbI3xDd5WxOgQss67B5QvRCwCObszSrv96O8oBF FMMWV1bZPbYs8PKSAierxEY6zpHXQmn8ONqmxr8tl3srRubC5FiYfsyvT EDvbzH3cwRDcxsUPyDnkvvRdtl+U1WCxV7MP7GuD+F8z0dk3tROoKpX5O IxglV7cemT3GyjIETFBHf9tZmKT03Yl08FVVpzkx6OuP6e8DPHW41FPX6 L+p7yUanKpa/OAHcZVbQF+cPSwaHXmTqC0KWoYT/NMIeJ/9qHGlnWPexd EwgcAUBQI8mIbCRLZOWWR4P9BhmIKk/eKUVIM4tzzMuFJxFBTDbUKJERy w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786750" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:30 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:27 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:24 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Date: Tue, 30 Aug 2022 11:17:55 +0100 Message-ID: <20220830101803.1456180-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220830_031836_425221_26E23523 X-CRM114-Status: GOOD ( 15.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey all, Some 6.1 targeted changes here. Firstly, two new dev kits (one first-party & one from Aries Embedded). They've been sitting in our vendor tree, so are being sent where they belong. Secondly, another release of our reference design for the Icicle kit is due in September. Usually these do not really change much for the devicetree, but this time around a pair of changes impact the memory map. The first of these is adding dma-ranges to the pcie controller. The controller had some issues to begin with & with the current reference design (v2022.05) would not work with mainline Linux nor has it since reference design v2021.08. A combination of the property, a change to the FPGA design & a small fix to the driver will get it working with mainline again. The other non-backwards compatible change to the reference design is moves of the peripherals instantiated in the fabric. Currently they are fairly spread out & a common complaint has been that this leaves little room in the fic3 section of the memory map for custom peripherals without removing the existing ones. This series depends on [0] so as not to add dtbs_check warnings. The fabric clock support is added by [1]. Thanks, Conor. Changes since v1: - made the polarberry part of an enum in patch 1 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/ 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/ Conor Dooley (7): dt-bindings: riscv: microchip: document icicle reference design dt-bindings: riscv: microchip: document the aries m100pfsevp riscv: dts: microchip: add pci dma ranges for the icicle kit riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: add a devicetree for aries' m100pfsevp Shravan Chippa (1): dt-bindings: riscv: microchip: document the sev kit Vattipalli Praveen (1): riscv: dts: microchip: add sevkit device tree .../devicetree/bindings/riscv/microchip.yaml | 21 ++- arch/riscv/boot/dts/microchip/Makefile | 3 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 42 ++++- .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 +- .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../dts/microchip/mpfs-m100pfsevp-emmc.dts | 37 +++++ .../dts/microchip/mpfs-m100pfsevp-sdcard.dts | 37 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dtsi | 155 ++++++++++++++++++ .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 ++++ .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ---- 12 files changed, 550 insertions(+), 41 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts