From patchwork Thu Sep 1 13:33:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 12962668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDF04ECAAD3 for ; Thu, 1 Sep 2022 13:38:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=g6nW/zRcJ0R2eBkg1BtSt3WAqRoULyZRsYrX1eQ8NbM=; b=y1c9IObDzZhGIM 5nRzuSB2zcfpYRsE9Kv+d5GKj1WT1gSXC9sahOpX72xc6dj9wYwCKN7r7ChE4isL7/XP/zYtEIoaz GMGYU/LMz4chw7fk7Py+ixow8wMrV3Na85cjv7268hrdMtDOVicHxVG++WJxIhlZNatejGDSm6thJ LSifod7oUHgrvfeAwY0blPLz368aHcXEHtPEfR58Q8SKno/77hi/wpSE/xXvfMuK/sV8uVDrOqLTD OAcC/ejyzi7dok9Y1Ck2O2qZ5WRyJgHKyt1ob5C55GG95sceoJ70NpBLyCzj89PwX9pT571HVnJ67 IQf6uYp/sxCvqeso+HrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTkON-00C7bI-Ob; Thu, 01 Sep 2022 13:37:59 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTkLY-00C5sb-8E for linux-riscv@lists.infradead.org; Thu, 01 Sep 2022 13:35:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662039304; x=1693575304; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=oIe8AzrscvcaqCgOhFdaYnxfcYRkv0jUW4Vfl5AOtxw=; b=BU3Fhpq7vm5IEHR1NfC6zw/pSeaL7TA5iS4aGmmtg9dQeCLl9VT/UFIe sLE/JEimgjIAv34YCVrBZTOfN1ZJLRprCnk6SlO5NoVPgKpIYY9g2tHjW uGZM+XmDLYveTQpjnRSyftkNebdaFxk5YJ2ZAQh9ETgY8Q153LCrnhuez zWhIc9e7urZNnryXGvi4s47ZN33dzoZRJMaLzpVyDT3ZvJH+YiRlpqqIM jDXgSy4ChEOaqS5UXdq/fOE8aL0S/wse4ohFKoKQ24KJCwnoRdy3cmeL6 yFfCvqrV5mxfwOlHanywqtpijMiBZh5W9PrRrjgMIMppYgLoHQIKGp0Sy w==; X-IronPort-AV: E=Sophos;i="5.93,280,1654585200"; d="scan'208";a="175197533" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2022 06:34:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 1 Sep 2022 06:34:45 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 1 Sep 2022 06:34:42 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v3 0/9] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Date: Thu, 1 Sep 2022 14:33:55 +0100 Message-ID: <20220901133403.3392291-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220901_063504_446053_8D027190 X-CRM114-Status: GOOD ( 15.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hey all, Some 6.1 targeted changes here. Firstly, two new dev kits (one first-party & one from Aries Embedded). They've been sitting in our vendor tree, so are being sent where they belong. Secondly, another release of our reference design for the Icicle kit is due in September. Usually these do not really change much for the devicetree, but this time around a pair of changes impact the memory map. The first of these is adding dma-ranges to the pcie controller. The controller had some issues to begin with & with the current reference design (v2022.05) would not work with mainline Linux nor has it since reference design v2021.08. A combination of the property, a change to the FPGA design & a small fix to the driver will get it working with mainline again. The other non-backwards compatible change to the reference design is moves of the peripherals instantiated in the fabric. Currently they are fairly spread out & a common complaint has been that this leaves little room in the fic3 section of the memory map for custom peripherals without removing the existing ones. This series depends on [0] so as not to add dtbs_check warnings. The fabric clock support is added by [1]. Thanks, Conor. Changes since v2: - drop the sd & emmc versions of the aries devicetree - remove a extra newline Changes since v1: - made the polarberry part of an enum in patch 1 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/ 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/ Conor Dooley (7): dt-bindings: riscv: microchip: document icicle reference design dt-bindings: riscv: microchip: document the aries m100pfsevp riscv: dts: microchip: add pci dma ranges for the icicle kit riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: add a devicetree for aries' m100pfsevp Shravan Chippa (1): dt-bindings: riscv: microchip: document the sev kit Vattipalli Praveen (1): riscv: dts: microchip: add sevkit device tree .../devicetree/bindings/riscv/microchip.yaml | 20 +- arch/riscv/boot/dts/microchip/Makefile | 2 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 42 +++- .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 +- .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++ .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++ .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 --- 10 files changed, 498 insertions(+), 41 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts