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[v5,00/10] New PolarFire SoC devkit devicetrees & 22.09 reference design updates

Message ID 20220916112645.567794-1-conor.dooley@microchip.com (mailing list archive)
Headers show
Series New PolarFire SoC devkit devicetrees & 22.09 reference design updates | expand

Message

Conor Dooley Sept. 16, 2022, 11:26 a.m. UTC
Hey all,

Some 6.1 targeted changes here.
Firstly, two new dev kits (one first-party & one from Aries Embedded).
They've been sitting in our vendor tree, so are being sent where they
belong.

Secondly, another release of our reference design for the Icicle kit
is due in September. Usually these do not really change much for the
devicetree, but this time around a pair of changes impact the memory
map.

The first of these is adding dma-ranges to the pcie controller. The
controller had some issues to begin with & with the current reference
design (v2022.05) would not work with mainline Linux nor has it since
reference design v2021.08. A combination of the property, a change
to the FPGA design & a small fix to the driver will get it working
with mainline again. The other non-backwards compatible change to the
reference design is moves of the peripherals instantiated in the
fabric. Currently they are fairly spread out & a common complaint has
been that this leaves little room in the fic3 section of the memory map
for custom peripherals without removing the existing ones.

This series depends on [0] so as not to add dtbs_check warnings. The
fabric clock support is added by [1].

Thanks,
Conor.

Changes since v4:
- fix the incompatible interrupts on m100pfsevp

Changes since v3:
- add an extra patch reducing the fic3 clock rate

Changes since v2:
- drop the sd & emmc versions of the aries devicetree
- remove a extra newline

Changes since v1:
- made the polarberry part of an enum in patch 1

0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/

Conor Dooley (8):
  dt-bindings: riscv: microchip: document icicle reference design
  dt-bindings: riscv: microchip: document the aries m100pfsevp
  riscv: dts: microchip: add pci dma ranges for the icicle kit
  riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
  riscv: dts: microchip: icicle: update pci address properties
  riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
  riscv: dts: microchip: reduce the fic3 clock rate
  riscv: dts: microchip: add a devicetree for aries' m100pfsevp

Shravan Chippa (1):
  dt-bindings: riscv: microchip: document the sev kit

Vattipalli Praveen (1):
  riscv: dts: microchip: add sevkit device tree

 .../devicetree/bindings/riscv/microchip.yaml  |  20 +-
 arch/riscv/boot/dts/microchip/Makefile        |   2 +
 .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  44 ++++-
 .../boot/dts/microchip/mpfs-icicle-kit.dts    |   3 +-
 .../dts/microchip/mpfs-m100pfs-fabric.dtsi    |  45 +++++
 .../boot/dts/microchip/mpfs-m100pfsevp.dts    | 179 ++++++++++++++++++
 .../dts/microchip/mpfs-polarberry-fabric.dtsi |  29 +++
 .../dts/microchip/mpfs-sev-kit-fabric.dtsi    |  45 +++++
 .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  29 ---
 10 files changed, 499 insertions(+), 42 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts

Comments

Conor Dooley Sept. 19, 2022, 6:22 p.m. UTC | #1
On Fri, Sep 16, 2022 at 12:26:36PM +0100, Conor Dooley wrote:
> Hey all,
> 
> Some 6.1 targeted changes here.
> Firstly, two new dev kits (one first-party & one from Aries Embedded).
> They've been sitting in our vendor tree, so are being sent where they
> belong.
> 
> Secondly, another release of our reference design for the Icicle kit
> is due in September. Usually these do not really change much for the
> devicetree, but this time around a pair of changes impact the memory
> map.
> 
> The first of these is adding dma-ranges to the pcie controller. The
> controller had some issues to begin with & with the current reference
> design (v2022.05) would not work with mainline Linux nor has it since
> reference design v2021.08. A combination of the property, a change
> to the FPGA design & a small fix to the driver will get it working
> with mainline again. The other non-backwards compatible change to the
> reference design is moves of the peripherals instantiated in the
> fabric. Currently they are fairly spread out & a common complaint has
> been that this leaves little room in the fic3 section of the memory map
> for custom peripherals without removing the existing ones.
> 
> This series depends on [0] so as not to add dtbs_check warnings. The
> fabric clock support is added by [1].

I've pushed this series to dt-for-next:
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=dt-for-next

There's a minor conflict with dt-fixes as that branch deletes a property
from the pcie dt node which is moved in this series. I deleted the
property as I moved it in this series so the fix will be to take the
version in dt-for-next instead.

> 
> Thanks,
> Conor.
> 
> Changes since v4:
> - fix the incompatible interrupts on m100pfsevp
> 
> Changes since v3:
> - add an extra patch reducing the fic3 clock rate
> 
> Changes since v2:
> - drop the sd & emmc versions of the aries devicetree
> - remove a extra newline
> 
> Changes since v1:
> - made the polarberry part of an enum in patch 1
> 
> 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/
> 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/
> 
> Conor Dooley (8):
>   dt-bindings: riscv: microchip: document icicle reference design
>   dt-bindings: riscv: microchip: document the aries m100pfsevp
>   riscv: dts: microchip: add pci dma ranges for the icicle kit
>   riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
>   riscv: dts: microchip: icicle: update pci address properties
>   riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
>   riscv: dts: microchip: reduce the fic3 clock rate
>   riscv: dts: microchip: add a devicetree for aries' m100pfsevp
> 
> Shravan Chippa (1):
>   dt-bindings: riscv: microchip: document the sev kit
> 
> Vattipalli Praveen (1):
>   riscv: dts: microchip: add sevkit device tree
> 
>  .../devicetree/bindings/riscv/microchip.yaml  |  20 +-
>  arch/riscv/boot/dts/microchip/Makefile        |   2 +
>  .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  44 ++++-
>  .../boot/dts/microchip/mpfs-icicle-kit.dts    |   3 +-
>  .../dts/microchip/mpfs-m100pfs-fabric.dtsi    |  45 +++++
>  .../boot/dts/microchip/mpfs-m100pfsevp.dts    | 179 ++++++++++++++++++
>  .../dts/microchip/mpfs-polarberry-fabric.dtsi |  29 +++
>  .../dts/microchip/mpfs-sev-kit-fabric.dtsi    |  45 +++++
>  .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  29 ---
>  10 files changed, 499 insertions(+), 42 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi
>  create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
> 
> -- 
> 2.36.1
>