From patchwork Tue Oct 11 23:18:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13004544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1EEADC433FE for ; Tue, 11 Oct 2022 23:23:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=OpUol32Yp8g+sPrfzynLSd7t/d2RyHaR1uVDcjcyfJM=; b=MPiR3pVt1XRs1b 80mJhW2dstboCzmsTandZYvMHwcNCm2BOK/bLsfdctyJrg7YclmVmN/+C6uHsFG2jtDX4BKxIQgQt qNPrsanNoMo2Ukdsft7bjKz40lu2MMlR5YE2xhpaQy78/dngfSwBZJqxfzvnzZ42nLutLvf0tz3Pu k7pxaiI8NXGnS72XLsfLd/NPJxrTtqIIPq3kllLZeXw72ca/+J4tOr8cPNtQZuHYMWxl0NO1Wo46B 8BK/v/gQALtUtowP5EwQMhQiMomte8ChsC4ndNhz6CIVPCYNufSsOE+AnfRV4vvz/bYRbTKtM35ct qZ1FF+4Lt7JNYG+dFmow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oiOaN-006B1f-6O; Tue, 11 Oct 2022 23:22:55 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oiOWU-0069Au-WF for linux-riscv@lists.infradead.org; Tue, 11 Oct 2022 23:18:56 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oiOWK-0003i7-1R; Wed, 12 Oct 2022 01:18:44 +0200 From: Heiko Stuebner To: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor.Dooley@microchip.com, samuel@sholland.org, Heiko Stuebner Subject: [PATCH v6 0/2] riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores Date: Wed, 12 Oct 2022 01:18:39 +0200 Message-Id: <20221011231841.2951264-1-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221011_161855_073950_C2AD6AA0 X-CRM114-Status: GOOD ( 10.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The PMU on T-Head C9xx cores is quite similar to the SSCOFPMF extension but not completely identical, so this series changes in v6: - follow Anup's suggestion and hook into the (pending) cpuinfo patch [2] instead of modifying the core sbi_get_* functions changes in v5: - add received Reviews - fix sbi caching wrt. negative values (Drew) - add comment about specific c9xx arch- and imp-ids (Conor) changes in v4: - add new patch to cache sbi mvendor, march and mimp-ids (Atish) - errata dependencies in one line (Conor) - make driver detection conditional on CONFIG_ERRATA_THEAD_PMU too (Atish) changes in v3: - improve commit message (Atish, Conor) - IS_ENABLED and BIT() in errata probe (Conor) The change depends on my cpufeature/t-head errata probe cleanup series [1]. changes in v2: - use alternatives for the CSR access - make the irq num selection a bit nicer There is of course a matching opensbi-part whose most recent implementation can be found on [0]. [0] https://patchwork.ozlabs.org/project/opensbi/cover/20221004164227.1381825-1-heiko@sntech.de [1] https://lore.kernel.org/all/20220905111027.2463297-1-heiko@sntech.de/ [2] https://lore.kernel.org/r/20220727043829.151794-1-apatel@ventanamicro.com Heiko Stuebner (2): RISC-V: Cache SBI vendor values drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores arch/riscv/Kconfig.erratas | 13 +++++++++++ arch/riscv/errata/thead/errata.c | 19 ++++++++++++++++ arch/riscv/include/asm/errata_list.h | 16 ++++++++++++- arch/riscv/include/asm/sbi.h | 5 ++++ arch/riscv/kernel/cpu.c | 30 +++++++++++++++++++++--- drivers/perf/riscv_pmu_sbi.c | 34 ++++++++++++++++++++-------- 6 files changed, 103 insertions(+), 14 deletions(-)