From patchwork Tue Nov 1 14:33:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13026971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3062AC433FE for ; Tue, 1 Nov 2022 14:34:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=M8RkDjPxbfl4InXSLar0xRsJlSont4eW73BX284lLto=; b=LuK2L1S8BjvhSd zDTpUbsKPByHr4MgVV2JWMfv1t1x9MbUTDW0oWNl34pxT5fqGsTUWAfn0x3aR/gj9V24SWFNSor2Q uvwTf3zEDA/oMxdH6V8PnDgIrOB0D5q3To/hhFvol3NHCi5OaLMVnEzJXsIYfLESPVOetWeSNN6F1 gUGvWZmPjvGuc84Sa0NbJmf/PtkDHvb2VZV2p2upLKoW4ROW6IyGN4WC5lQ9S3fvtv8yO1BsNWm4R deNVky+E8OzGbyDsJ2932G3ex6Fw7uWgqP6wuAQBZ4mOcaSBy55OxxD2h4tAOaFfzY3wDjcO3jHAl 3pQyhSAB3SgqGs6A8DbQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1opsLe-005VBM-92; Tue, 01 Nov 2022 14:34:38 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1opsLb-005VAi-CC for linux-riscv@lists.infradead.org; Tue, 01 Nov 2022 14:34:37 +0000 Received: by mail-pl1-x631.google.com with SMTP id k7so4008210pll.6 for ; Tue, 01 Nov 2022 07:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=bzrUAtNLPZtva+XCQ1PJ1UKO7iIk8iXap37Oxcyeu5I=; b=fyS2W+arSy0GY5JgumfUxcS6nkiXA/qIpfsdeHJ9WAwPuV35UGueycE4MWQGNkwZ3X LXWaOAijKFEUPIfG66XZLTIlzWbxfaZTwLkHM2P0RLbKuogEamt70YHTzLfG2qqbzuXu I7A1tSb4/56x21eWdiBE/ByFtvhB5n7kPSuEVpiGC1cpS4AsSj46i6feKK/ew9y1nhdc h81mf2LvGxzu5oUHPGwlVb8uWa5bQLDM+Umc4WxPtAPnTuvN7lI0XbQqdlGccpfv/Bqy 3kMY1/u0JSEQ8H7PihMFnidq0fURB2Btk6jIL9IX6ZssUYCDstxM1ZahycFBVE5VNt9O WMeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bzrUAtNLPZtva+XCQ1PJ1UKO7iIk8iXap37Oxcyeu5I=; b=FeF0k45F59uTPhjPnabgkbE7daKQPLA3FMGoRPvLO8dxtFaN3G4rHVHYmRiJtLMdZk kQ2M7/+GUKYr1FkVwbVWVgTMqaJ9X89VbQAGllWLWpk2gI3ey0YmX8ubQYN1apCqmx9d vPFzZiyfPrTrAdZmA/8lqOFcIATx8VVmTkUJGs0FpxiHCu6igxv5a7lHPVcFdMs46TpP uQsRyAPZO+39c7SMJzWMqVWTmyN6PhPVffKM2gJGirvvHTdHjTsUicsDsPDlf3P9DOIe 7csS7YGP/Q4PUP2pMJZBssrAsjvEp6JHjItUE3zmebGUpQ0daFPVfPjYUHjP8OPTuI41 ClSQ== X-Gm-Message-State: ACrzQf3y8cnofEhzkzCbwVhEzT4df73geect2OsLs6/jS5uimOBh440x Tzl9oKxJ3qwb4AMYdL5kx8wzAw== X-Google-Smtp-Source: AMsMyM5yJSXbt3KfVv4pviMIXwN89iogpmlTwT/XCR4Mr4uXwQA6rTwiHcFQ9ciVAUTHQiws4FZheg== X-Received: by 2002:a17:90a:af83:b0:213:d08f:a47f with SMTP id w3-20020a17090aaf8300b00213d08fa47fmr14468363pjq.28.1667313273364; Tue, 01 Nov 2022 07:34:33 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.52]) by smtp.gmail.com with ESMTPSA id o20-20020a170903009400b0018685aaf41dsm6449055pld.18.2022.11.01.07.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Nov 2022 07:34:33 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v10 0/7] RISC-V IPI Improvements Date: Tue, 1 Nov 2022 20:03:53 +0530 Message-Id: <20221101143400.690000-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221101_073435_438644_3D4E4057 X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series aims to improve IPI support in Linux RISC-V in following ways: 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V specific hooks. This also makes Linux RISC-V IPI support aligned with other architectures. 2) Remote TLB flushes and icache flushes should prefer local IPIs instead of SBI calls whenever we have specialized hardware (such as RISC-V AIA IMSIC and RISC-V SWI) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. These patches were originally part of the "Linux RISC-V ACLINT Support" series but this now a separate series so that it can be merged independently of the "Linux RISC-V ACLINT Support" series. (Refer, https://lore.kernel.org/lkml/20211007123632.697666-1-anup.patel@wdc.com/) These patches are also a preparatory patches for the up-coming: 1) Linux RISC-V AIA support 2) Linux RISC-V SWI support These patches can also be found in riscv_ipi_imp_v10 branch at: https://github.com/avpatel/linux.git Changes since v9: - Rebased on Linux-6.1-rc3 - Updated header comment block of ipi-mux.c in PATCH3 - Use a struct for global data of ipi-mux.c in PATCH3 - Add per-CPU temp cpumask for sending IPIs in PATCH3 - Drop the use of fwspec in PATCH3 - Use static key for ipi_mux_pre_handle() and ipi_mux_post_handle() in PATCH3 - Remove redundant pr_warn_ratelimited() called by ipi_mux_process() in PATCH3 - Remove CPUHP thingy from ipi_mux_create() in PATCH3 Changes since v8: - Rebased on Linux-6.0-rc3 - Use dummy percpu data as parameter for request_percpu_irq() in PATCH4. Changes since v7: - Rebased on Linux-6.0-rc1 - Use atomic operations to track per-CPU pending and enabled IPIs in PATCH3. (Note: this is inspired from IPI muxing implemented in drivers/irqchip/irq-apple-aic.c) - Made "struct ipi_mux_ops" (added by PATCH3) flexible so that drivers/irqchip/irq-apple-aic.c can adopt it in future. Changes since v6: - Rebased on Linux-5.19-rc7 - Added documentation for struct ipi_mux_ops in PATCH3 - Dropped dummy irq_mask()/unmask() in PATCH3 - Added const for "ipi_mux_chip" in PATCH3 - Removed "type" initialization from ipi_mux_domain_alloc() in PATCH3 - Dropped translate() from "ipi_mux_domain_ops" in PATCH3 - Improved barrier documentation in ipi_mux_process() of PATCH3 - Added percpu check in ipi_mux_create() for parent_virq of PATCH3 - Added nr_ipi parameter in ipi_mux_create() of PATCH3 Changes since v5: - Rebased on Linux-5.18-rc3 - Used kernel doc style in PATCH3 - Removed redundant loop in ipi_mux_process() of PATCH3 - Removed "RISC-V" prefix form ipi_mux_chip.name of PATCH3 - Removed use of "this patch" in PATCH3 commit description - Addressed few other nit comments in PATCH3 Changes since v4: - Rebased on Linux-5.17 - Includes new PATCH3 which adds mechanism to multiplex a single HW IPI Changes since v3: - Rebased on Linux-5.17-rc6 - Updated PATCH2 to not export riscv_set_intc_hwnode_fn() - Simplified riscv_intc_hwnode() in PATCH2 Changes since v2: - Rebased on Linux-5.17-rc4 - Updated PATCH2 to not create synthetic INTC fwnode and instead provide a function which allows drivers to directly discover INTC fwnode Changes since v1: - Use synthetic fwnode for INTC instead of irq_set_default_host() in PATCH2 Anup Patel (7): RISC-V: Clear SIP bit only when using SBI IPI operations irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode genirq: Add mechanism to multiplex a single HW IPI RISC-V: Treat IPIs as normal Linux IRQs RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Use IPIs for remote icache flush when possible arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 4 + arch/riscv/include/asm/sbi.h | 7 + arch/riscv/include/asm/smp.h | 49 ++++-- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/irq.c | 21 ++- arch/riscv/kernel/sbi-ipi.c | 80 +++++++++ arch/riscv/kernel/sbi.c | 11 -- arch/riscv/kernel/smp.c | 166 ++++++++++--------- arch/riscv/kernel/smpboot.c | 5 +- arch/riscv/mm/cacheflush.c | 5 +- arch/riscv/mm/tlbflush.c | 93 +++++++++-- drivers/clocksource/timer-clint.c | 43 +++-- drivers/irqchip/irq-riscv-intc.c | 60 +++---- include/linux/irq.h | 18 +++ kernel/irq/Kconfig | 5 + kernel/irq/Makefile | 1 + kernel/irq/ipi-mux.c | 260 ++++++++++++++++++++++++++++++ 19 files changed, 667 insertions(+), 167 deletions(-) create mode 100644 arch/riscv/kernel/sbi-ipi.c create mode 100644 kernel/irq/ipi-mux.c