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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id k14-20020a056870350e00b0013d9bd4ad2esm787353oah.12.2022.11.10.20.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 20:42:43 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH 0/9] Linux RISC-V AIA Support Date: Fri, 11 Nov 2022 10:11:58 +0530 Message-Id: <20221111044207.1478350-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221110_204244_718049_FFC670E9 X-CRM114-Status: GOOD ( 10.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The RISC-V AIA specification is now frozen as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv/riscv-aia/releases/download/1.0-RC1/riscv-interrupts-1.0-RC1.pdf At a high-level, the AIA specification adds three things: 1) AIA CSRs - Improved local interrupt support 2) Incoming Message Signaled Interrupt Controller (IMSIC) - Per-HART MSI controller - Support MSI virtualization - Support IPI along with virtualization 3) Advanced Platform-Level Interrupt Controller (APLIC) - Wired interrupt controller - In MSI-mode, converts wired interrupt into MSIs (i.e. MSI generator) - In Direct-mode, injects external interrupts directly into HARTs For an overview of the AIA specification, refer the recent AIA virtualization talk at KVM Forum 2022: https://static.sched.com/hosted_files/kvmforum2022/a1/AIA_Virtualization_in_KVM_RISCV_final.pdf https://www.youtube.com/watch?v=r071dL8Z0yo This series adds required Linux irqchip drivers for AIA and it depends on the recent "RISC-V IPI Improvements". (Refer, https://lore.kernel.org/lkml/20221101143400.690000-1-apatel@ventanamicro.com/t/) To test this series, use QEMU v7.1 (or higher) and OpenSBI v1.1 (or higher). These patches can also be found in the riscv_aia_v1 branch at: https://github.com/avpatel/linux.git Anup Patel (9): RISC-V: Add AIA related CSR defines RISC-V: Detect AIA CSRs from ISA string irqchip/riscv-intc: Add support for RISC-V AIA dt-bindings: Add RISC-V incoming MSI controller bindings irqchip: Add RISC-V incoming MSI controller driver dt-bindings: Add RISC-V advanced PLIC bindings irqchip: Add RISC-V advanced PLIC driver RISC-V: Select APLIC and IMSIC drivers for QEMU virt machine MAINTAINERS: Add entry for RISC-V AIA drivers .../interrupt-controller/riscv,aplic.yaml | 136 ++ .../interrupt-controller/riscv,imsic.yaml | 174 +++ MAINTAINERS | 12 + arch/riscv/Kconfig.socs | 2 + arch/riscv/include/asm/csr.h | 92 ++ arch/riscv/include/asm/hwcap.h | 8 + arch/riscv/kernel/cpu.c | 2 + arch/riscv/kernel/cpufeature.c | 2 + drivers/irqchip/Kconfig | 32 +- drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-riscv-aplic.c | 656 +++++++++ drivers/irqchip/irq-riscv-imsic.c | 1207 +++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 37 +- include/linux/irqchip/riscv-aplic.h | 117 ++ include/linux/irqchip/riscv-imsic.h | 92 ++ 15 files changed, 2564 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsic.yaml create mode 100644 drivers/irqchip/irq-riscv-aplic.c create mode 100644 drivers/irqchip/irq-riscv-imsic.c create mode 100644 include/linux/irqchip/riscv-aplic.h create mode 100644 include/linux/irqchip/riscv-imsic.h