From patchwork Tue Nov 29 14:24:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13058634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DA19C4321E for ; Tue, 29 Nov 2022 14:25:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=I4xooZT2+qMR5w90rFHz64k02Y5E802JVda8LNbZhqA=; b=lMlNDwF2/4rY23 Q4JlTIKxZkD/N82b9DSuxwbIO+NMhV8F2uO4Vthgx9x8LPZYUrrkzFZtH4EJl4C9yyuUnX/EEVtVi ai/oQ44en0pmaTYO+r81y8wGw/rXS0QCzrZrpsHKQAfXGMBre1f0i1K0I1DYb+e1aN9etz8d+nL/U Njq57Zdg2fcburnR/T/9g2C/Qme8Bl8V5KLL9dtwX+b8kBtJZyQr/FpVpvqv3jwhncGGidmO4aRaY aPkI8vfK7QlEQTfCgDJKHts5LVKSpJlaGn+tic4e0a8874SKCmQg+phbqtoMhCIK5+BFEI3prhO4F j8FKYgCrFtRQl7V0px4Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01Xq-009DmP-3o; Tue, 29 Nov 2022 14:25:10 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p01Xl-009DgN-5Y for linux-riscv@lists.infradead.org; Tue, 29 Nov 2022 14:25:07 +0000 Received: by mail-pl1-x630.google.com with SMTP id b21so13542320plc.9 for ; Tue, 29 Nov 2022 06:24:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=siIjiVH9KFJA1s2eaItHJT53l6QhYo3Iz+saYCu0w3I=; b=RItEu2uqWXy8hsPQriDTJ+h3EQ8pjFjRwPc5TpUTApuocrkQYvxlo2fH2Ouw8Rc5lA W0NkSLAkMAlnh6HEmSkyD/uqeoi8OLS9LYTkwmZGxxUe+/SEKLLy86qeWIpNq3jqnzBV u7mFrqaTZ5Al0oMAxS0VlXsvj3cgkryep26Cd4Fd36P+PcKZL2Joahx7yUoD1LTzBg5k 0BKmCxvee7i+Su2VQmk8CS4Rn67ZuUzSnCNozGqgdqex/qolnVwsvD+7FgaXws8leadq x+9kJfSR4GZitGQMs5GTrlliaEygMVT44L7hu2gnVHIoUrby6CMZRFhf/pEaX8xu4+GR bycg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=siIjiVH9KFJA1s2eaItHJT53l6QhYo3Iz+saYCu0w3I=; b=gNvYRFOkaw6tayUMddRjjEO70k4JQAuaKUvIc0e6jt4jjDgQbaNWFZIsmHZlgU7OU5 LRs5VNQYel++Ods/JBT/wFlaeeOJSISOmepxseMPDPTSEVEh0smWTJxvPUUCAOGs4Eux HS+u6/yYg/biSwGHX6f809OdWLLWikd1ufmuhrAV8VbPu9KXBxM2TQoJsNdC6v5kzUql hXAZBZMS/YYjGbA5QpJJxUJ0t7usFgaDITOk2apN/RWJ7IrMqQUK6u4oiG7L0DjdKc9F 0etBOLprG8+Kg85yHRzXvZecxV/YvpWZiwlIMr+h2FO6KUMLbIELbUbGLTeWnu9Ud50t zwHg== X-Gm-Message-State: ANoB5pnYQZN7K0xGRwYJnEcHrptmLAgp/Nosu7C84gfQVWNJHvtb9yuu 9V7OCp8Bv4BK5HO+Yo0hl0lDrQ== X-Google-Smtp-Source: AA0mqf7QeCbOjuvcB9jwqku7pWS9Tt3TUF580uEABK0TXs86dVlES9sWf7YkGMTWZ4dg008T0jhFjA== X-Received: by 2002:a17:902:b40a:b0:188:635d:4b43 with SMTP id x10-20020a170902b40a00b00188635d4b43mr41408597plr.69.1669731897488; Tue, 29 Nov 2022 06:24:57 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.84.98]) by smtp.gmail.com with ESMTPSA id l12-20020a170903120c00b00176a2d23d1asm11039076plh.56.2022.11.29.06.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 06:24:57 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v13 0/7] RISC-V IPI Improvements Date: Tue, 29 Nov 2022 19:54:42 +0530 Message-Id: <20221129142449.886518-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_062505_285628_E686165E X-CRM114-Status: GOOD ( 17.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series aims to improve IPI support in Linux RISC-V in following ways: 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V specific hooks. This also makes Linux RISC-V IPI support aligned with other architectures. 2) Remote TLB flushes and icache flushes should prefer local IPIs instead of SBI calls whenever we have specialized hardware (such as RISC-V AIA IMSIC and RISC-V SWI) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. These patches were originally part of the "Linux RISC-V ACLINT Support" series but this now a separate series so that it can be merged independently of the "Linux RISC-V ACLINT Support" series. (Refer, https://lore.kernel.org/lkml/20211007123632.697666-1-anup.patel@wdc.com/) These patches are also a preparatory patches for the up-coming: 1) Linux RISC-V AIA support 2) Linux RISC-V SWI support These patches can also be found in riscv_ipi_imp_v13 branch at: https://github.com/avpatel/linux.git Changes since v12: - Rebased on Linux-6.1-rc7 - Bring-back the IPI optimization in ipi_mux_send_mask() for PATCH3 - Call ipi_mux_send() for one target CPU at a time in PATCH3 Changes since v11: - Removed ipi_mux_pre/post_handle() callbacks in PATCH3 - Removed sturct ipi_mux_ops in PATCH3 - Removed parent_virq and data pointer from everywhere in PATCH3 - Removed struct ipi_mux_control in PATCH3 - Improved function signature of ipi_mux_send() callback in PATCH3 - Used unsigned type with atomic operation in PATCH3 Changes since v10: - Rebased on Linux-6.1-rc5 - Drop the "!(pending & ibit)" check in ipi_mux_send_mask() of PATCH3 - Disable local interrupts in ipi_mux_send_mask() of PATCH3 because we can be preempted while using a per-CPU temporary variable. Changes since v9: - Rebased on Linux-6.1-rc3 - Updated header comment block of ipi-mux.c in PATCH3 - Use a struct for global data of ipi-mux.c in PATCH3 - Add per-CPU temp cpumask for sending IPIs in PATCH3 - Drop the use of fwspec in PATCH3 - Use static key for ipi_mux_pre_handle() and ipi_mux_post_handle() in PATCH3 - Remove redundant pr_warn_ratelimited() called by ipi_mux_process() in PATCH3 - Remove CPUHP thingy from ipi_mux_create() in PATCH3 Changes since v8: - Rebased on Linux-6.0-rc3 - Use dummy percpu data as parameter for request_percpu_irq() in PATCH4. Changes since v7: - Rebased on Linux-6.0-rc1 - Use atomic operations to track per-CPU pending and enabled IPIs in PATCH3. (Note: this is inspired from IPI muxing implemented in drivers/irqchip/irq-apple-aic.c) - Made "struct ipi_mux_ops" (added by PATCH3) flexible so that drivers/irqchip/irq-apple-aic.c can adopt it in future. Changes since v6: - Rebased on Linux-5.19-rc7 - Added documentation for struct ipi_mux_ops in PATCH3 - Dropped dummy irq_mask()/unmask() in PATCH3 - Added const for "ipi_mux_chip" in PATCH3 - Removed "type" initialization from ipi_mux_domain_alloc() in PATCH3 - Dropped translate() from "ipi_mux_domain_ops" in PATCH3 - Improved barrier documentation in ipi_mux_process() of PATCH3 - Added percpu check in ipi_mux_create() for parent_virq of PATCH3 - Added nr_ipi parameter in ipi_mux_create() of PATCH3 Changes since v5: - Rebased on Linux-5.18-rc3 - Used kernel doc style in PATCH3 - Removed redundant loop in ipi_mux_process() of PATCH3 - Removed "RISC-V" prefix form ipi_mux_chip.name of PATCH3 - Removed use of "this patch" in PATCH3 commit description - Addressed few other nit comments in PATCH3 Changes since v4: - Rebased on Linux-5.17 - Includes new PATCH3 which adds mechanism to multiplex a single HW IPI Changes since v3: - Rebased on Linux-5.17-rc6 - Updated PATCH2 to not export riscv_set_intc_hwnode_fn() - Simplified riscv_intc_hwnode() in PATCH2 Changes since v2: - Rebased on Linux-5.17-rc4 - Updated PATCH2 to not create synthetic INTC fwnode and instead provide a function which allows drivers to directly discover INTC fwnode Changes since v1: - Use synthetic fwnode for INTC instead of irq_set_default_host() in PATCH2 Anup Patel (7): RISC-V: Clear SIP bit only when using SBI IPI operations irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode genirq: Add mechanism to multiplex a single HW IPI RISC-V: Treat IPIs as normal Linux IRQs RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Use IPIs for remote icache flush when possible arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 4 + arch/riscv/include/asm/sbi.h | 10 +- arch/riscv/include/asm/smp.h | 49 +++++--- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/irq.c | 21 +++- arch/riscv/kernel/sbi-ipi.c | 81 +++++++++++++ arch/riscv/kernel/sbi.c | 100 +++------------- arch/riscv/kernel/smp.c | 166 +++++++++++++------------ arch/riscv/kernel/smpboot.c | 5 +- arch/riscv/mm/cacheflush.c | 5 +- arch/riscv/mm/tlbflush.c | 93 +++++++++++--- drivers/clocksource/timer-clint.c | 65 +++++++--- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-intc.c | 60 +++++----- include/linux/irq.h | 3 + kernel/irq/Kconfig | 5 + kernel/irq/Makefile | 1 + kernel/irq/ipi-mux.c | 193 ++++++++++++++++++++++++++++++ 20 files changed, 621 insertions(+), 247 deletions(-) create mode 100644 arch/riscv/kernel/sbi-ipi.c create mode 100644 kernel/irq/ipi-mux.c