| Message ID | 20221129143447.49714-1-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Ensure Zicbom has a valid block size | expand |
On Tue, 29 Nov 2022 15:34:44 +0100, Andrew Jones wrote: > When a DT puts zicbom in the isa string, but does not provide a block > size, ALT_CMO_OP() will attempt to do cache operations on address > zero since the start address will be ANDed with zero. We can't simply > BUG() in riscv_init_cbom_blocksize() when we fail to find a block > size because the failure will happen before logging works, leaving > users to scratch their heads as to why the boot hung. Instead, ensure > Zicbom is disabled and output an error which will hopefully alert > people that the DT needs to be fixed. While at it, add a check that > the block size is a power-of-2 too. > > [...] Applied, thanks! [1/3] RISC-V: Improve use of isa2hwcap[] https://git.kernel.org/palmer/c/78eda777d2f1 [2/3] RISC-V: Introduce riscv_isa_extension_check https://git.kernel.org/palmer/c/132cfeb2b7fd [3/3] RISC-V: Ensure Zicbom has a valid block size https://git.kernel.org/palmer/c/68dc0718407d Best regards,
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Tue, 29 Nov 2022 15:34:44 +0100 you wrote: > When a DT puts zicbom in the isa string, but does not provide a block > size, ALT_CMO_OP() will attempt to do cache operations on address > zero since the start address will be ANDed with zero. We can't simply > BUG() in riscv_init_cbom_blocksize() when we fail to find a block > size because the failure will happen before logging works, leaving > users to scratch their heads as to why the boot hung. Instead, ensure > Zicbom is disabled and output an error which will hopefully alert > people that the DT needs to be fixed. While at it, add a check that > the block size is a power-of-2 too. > > [...] Here is the summary with links: - [v3,1/3] RISC-V: Improve use of isa2hwcap[] https://git.kernel.org/riscv/c/78eda777d2f1 - [v3,2/3] RISC-V: Introduce riscv_isa_extension_check https://git.kernel.org/riscv/c/132cfeb2b7fd - [v3,3/3] RISC-V: Ensure Zicbom has a valid block size https://git.kernel.org/riscv/c/68dc0718407d You are awesome, thank you!
When a DT puts zicbom in the isa string, but does not provide a block size, ALT_CMO_OP() will attempt to do cache operations on address zero since the start address will be ANDed with zero. We can't simply BUG() in riscv_init_cbom_blocksize() when we fail to find a block size because the failure will happen before logging works, leaving users to scratch their heads as to why the boot hung. Instead, ensure Zicbom is disabled and output an error which will hopefully alert people that the DT needs to be fixed. While at it, add a check that the block size is a power-of-2 too. The first patch of the series is a cleanup of code that crossed the path of this work. The second patch prepares for isa ext. checking and the third finally does what this cover letter says. Thanks, drew v3: - Mostly just a friendly ping, but also rebased and picked up r-b's v2: - Unconditionally complain when we detect a problem with DT's cbom-block-size - A couple r-b's from Conor Andrew Jones (3): RISC-V: Improve use of isa2hwcap[] RISC-V: Introduce riscv_isa_extension_check RISC-V: Ensure Zicbom has a valid block size arch/riscv/kernel/cpufeature.c | 43 ++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 10 deletions(-)