From patchwork Thu Dec 1 13:01:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13061305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB344C43217 for ; Thu, 1 Dec 2022 13:07:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=BO04QXE/gOPIs/yKU+kWph2xPJhRkqGK4AICBrf66Ec=; b=livKfz+oDXDijX vz8Z0mcofdyQ+yX/Tu24Aq07MzPiQipqGz/Ngq48A42Vnv67E4WDrhCjx1DaRMkGugSbULvUulnjs gQQ2gN/SwA0Kcwx/M2m1baHKXlu6KOH1Xl4S1kkQVplNP+Zz8cnxpWV6U04U4UM+FKLKgrI8s4PQk WeqmgZYNXgyOhXv3vsz9syiv/hStVE4TXykZWMDaolYDLwEOk/0s+qFg7mRP0DBdnSaNvITCe7OL+ IDCixdlK2GvArt72N0upAJ2GZTpKP8PUenZOttQcWy3/GvPHV2JY3Qu8zeMtLfXjwosnpVSqyy9S/ HA/UYBwiLAdYghxEBWtw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0jHl-007aCX-99; Thu, 01 Dec 2022 13:07:29 +0000 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p0jCH-007SPU-6g for linux-riscv@lists.infradead.org; Thu, 01 Dec 2022 13:01:54 +0000 Received: by mail-pg1-x536.google.com with SMTP id 82so1648658pgc.0 for ; Thu, 01 Dec 2022 05:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=iGN3VL/XFnVBkPaM7c0HjkkPxAlIY56C6pEqxkaLsVI=; b=JRWrAp8pv7B0SuPanT2S5U0Gl2lpwtK8NYFWWI7a2f+xm7t/Ok8i2BuXx0BL/3SFHw Sa4HhlcaSlfsS6JUwKLvXFM22sLEyh65+AwvsN5MzbW10y+nCvw6ZAuv/Mn25r9z5iEH hkZCB80ZaREHd9Kb15AqDb6YFW7sE5cK+dsTUjpW5nLXUxDX0BTorPv9XywKu8JI1CAY zA3ue2VcJbkkitZpeKwFbLyjPXzzRaDyhSZ3wp+Xzfr1oR1R0fwvSkhLign7M2qxVaFq tsr1k1C4ErhZ/SDdyi5Jb/2+LSZBcMxWGf6IKIiZayjwBqIaPQeKH5KeQkstRU/xlIrE GwOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=iGN3VL/XFnVBkPaM7c0HjkkPxAlIY56C6pEqxkaLsVI=; b=RZagpDxD3u23NEXkbtChjhyYceN+aJ0dIpDtUzregwpJWtYJ4ARPd3oz3GWVZnv1Dw DjDZeX/Ox2y72Im3PsGBGHB/RSqBi9bpZm3R4ARvB6bngQ8d+pC3Kvdxl0cnYMHrfMy3 ZNCbyLNCls5sz6QdChXslvrYc/45VbL0mEBgCzGMDv2PX9K8P/QxhtJ+3a1eca/443sS wUHZld02y+8EzbLJWZN8k2+v447V5NdR0rUhoabdBbJKNvaeqyB3f4PUxMDW08ptmJNC 1frkXdw6C2y4SRkPE8Mc6b4WeLOyYn40dt3uUrj4BdeSr1xjTV0R+s0pZBeiYQW71G0H lC5w== X-Gm-Message-State: ANoB5pmJhKNWSJi7orHEOp73uenLnrKMrrRaTwZFOu0Cm+80f9G9Sq67 H/iB+FLb8Z9l6Pvjp75BBMEPQA== X-Google-Smtp-Source: AA0mqf61sisn+k2svr9kmDGtZMtFfy3Z+A1+tjC43OYDFaaWaKpPpOzR4oLwtDnCPW7PiNxL5Pl3qg== X-Received: by 2002:a63:d751:0:b0:46f:f87c:fb1a with SMTP id w17-20020a63d751000000b0046ff87cfb1amr43453753pgi.214.1669899705201; Thu, 01 Dec 2022 05:01:45 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.81.69]) by smtp.gmail.com with ESMTPSA id l4-20020a17090a384400b00212c27abcaesm4855856pjf.17.2022.12.01.05.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 05:01:44 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v14 0/8] RISC-V IPI Improvements Date: Thu, 1 Dec 2022 18:31:27 +0530 Message-Id: <20221201130135.1115380-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221201_050149_296845_4A3A3F42 X-CRM114-Status: GOOD ( 17.04 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series aims to improve IPI support in Linux RISC-V in following ways: 1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V specific hooks. This also makes Linux RISC-V IPI support aligned with other architectures. 2) Remote TLB flushes and icache flushes should prefer local IPIs instead of SBI calls whenever we have specialized hardware (such as RISC-V AIA IMSIC and RISC-V SWI) which allows S-mode software to directly inject IPIs without any assistance from M-mode runtime firmware. These patches were originally part of the "Linux RISC-V ACLINT Support" series but this now a separate series so that it can be merged independently of the "Linux RISC-V ACLINT Support" series. (Refer, https://lore.kernel.org/lkml/20211007123632.697666-1-anup.patel@wdc.com/) These patches are also a preparatory patches for the up-coming: 1) Linux RISC-V AIA support 2) Linux RISC-V SWI support These patches can also be found in riscv_ipi_imp_v14 branch at: https://github.com/avpatel/linux.git Changes since v13: - Included changes suggested by Marc Z in PATCH3 - Use chained handlers in PATCH4 - Added new PATCH8 to have empty irq_eoi() in RISC-V INTC driver. This avoids the unnecessary mask/unmask dance at time of handling interrupts. Changes since v12: - Rebased on Linux-6.1-rc7 - Bring-back the IPI optimization in ipi_mux_send_mask() for PATCH3 - Call ipi_mux_send() for one target CPU at a time in PATCH3 Changes since v11: - Removed ipi_mux_pre/post_handle() callbacks in PATCH3 - Removed sturct ipi_mux_ops in PATCH3 - Removed parent_virq and data pointer from everywhere in PATCH3 - Removed struct ipi_mux_control in PATCH3 - Improved function signature of ipi_mux_send() callback in PATCH3 - Used unsigned type with atomic operation in PATCH3 Changes since v10: - Rebased on Linux-6.1-rc5 - Drop the "!(pending & ibit)" check in ipi_mux_send_mask() of PATCH3 - Disable local interrupts in ipi_mux_send_mask() of PATCH3 because we can be preempted while using a per-CPU temporary variable. Changes since v9: - Rebased on Linux-6.1-rc3 - Updated header comment block of ipi-mux.c in PATCH3 - Use a struct for global data of ipi-mux.c in PATCH3 - Add per-CPU temp cpumask for sending IPIs in PATCH3 - Drop the use of fwspec in PATCH3 - Use static key for ipi_mux_pre_handle() and ipi_mux_post_handle() in PATCH3 - Remove redundant pr_warn_ratelimited() called by ipi_mux_process() in PATCH3 - Remove CPUHP thingy from ipi_mux_create() in PATCH3 Changes since v8: - Rebased on Linux-6.0-rc3 - Use dummy percpu data as parameter for request_percpu_irq() in PATCH4. Changes since v7: - Rebased on Linux-6.0-rc1 - Use atomic operations to track per-CPU pending and enabled IPIs in PATCH3. (Note: this is inspired from IPI muxing implemented in drivers/irqchip/irq-apple-aic.c) - Made "struct ipi_mux_ops" (added by PATCH3) flexible so that drivers/irqchip/irq-apple-aic.c can adopt it in future. Changes since v6: - Rebased on Linux-5.19-rc7 - Added documentation for struct ipi_mux_ops in PATCH3 - Dropped dummy irq_mask()/unmask() in PATCH3 - Added const for "ipi_mux_chip" in PATCH3 - Removed "type" initialization from ipi_mux_domain_alloc() in PATCH3 - Dropped translate() from "ipi_mux_domain_ops" in PATCH3 - Improved barrier documentation in ipi_mux_process() of PATCH3 - Added percpu check in ipi_mux_create() for parent_virq of PATCH3 - Added nr_ipi parameter in ipi_mux_create() of PATCH3 Changes since v5: - Rebased on Linux-5.18-rc3 - Used kernel doc style in PATCH3 - Removed redundant loop in ipi_mux_process() of PATCH3 - Removed "RISC-V" prefix form ipi_mux_chip.name of PATCH3 - Removed use of "this patch" in PATCH3 commit description - Addressed few other nit comments in PATCH3 Changes since v4: - Rebased on Linux-5.17 - Includes new PATCH3 which adds mechanism to multiplex a single HW IPI Changes since v3: - Rebased on Linux-5.17-rc6 - Updated PATCH2 to not export riscv_set_intc_hwnode_fn() - Simplified riscv_intc_hwnode() in PATCH2 Changes since v2: - Rebased on Linux-5.17-rc4 - Updated PATCH2 to not create synthetic INTC fwnode and instead provide a function which allows drivers to directly discover INTC fwnode Changes since v1: - Use synthetic fwnode for INTC instead of irq_set_default_host() in PATCH2 Anup Patel (8): RISC-V: Clear SIP bit only when using SBI IPI operations irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode genirq: Add mechanism to multiplex a single HW IPI RISC-V: Treat IPIs as normal Linux IRQs RISC-V: Allow marking IPIs as suitable for remote FENCEs RISC-V: Use IPIs for remote TLB flush when possible RISC-V: Use IPIs for remote icache flush when possible irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers arch/riscv/Kconfig | 2 + arch/riscv/include/asm/irq.h | 4 + arch/riscv/include/asm/sbi.h | 10 +- arch/riscv/include/asm/smp.h | 49 +++++--- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpu-hotplug.c | 3 +- arch/riscv/kernel/irq.c | 21 +++- arch/riscv/kernel/sbi-ipi.c | 77 ++++++++++++ arch/riscv/kernel/sbi.c | 100 +++------------ arch/riscv/kernel/smp.c | 166 +++++++++++++------------ arch/riscv/kernel/smpboot.c | 5 +- arch/riscv/mm/cacheflush.c | 5 +- arch/riscv/mm/tlbflush.c | 93 +++++++++++--- drivers/clocksource/timer-clint.c | 61 ++++++--- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-intc.c | 71 +++++++---- include/linux/irq.h | 3 + kernel/irq/Kconfig | 5 + kernel/irq/Makefile | 1 + kernel/irq/ipi-mux.c | 199 ++++++++++++++++++++++++++++++ 20 files changed, 633 insertions(+), 244 deletions(-) create mode 100644 arch/riscv/kernel/sbi-ipi.c create mode 100644 kernel/irq/ipi-mux.c