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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id a28-20020a63705c000000b00528513c6bbcsm9356535pgn.28.2023.07.15.08.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Jul 2023 08:00:38 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: vineetg@rivosinc.com, bjorn@kernel.org, greentime.hu@sifive.com, paul.walmsley@sifive.com, guoren@linux.alibaba.com, anup@brainfault.org, atishp@atishpatra.org, heiko.stuebner@vrull.eu, Andy Chiu , Albert Ou Subject: [v1, 0/6] riscv: support kernel-mode Vector Date: Sat, 15 Jul 2023 15:00:26 +0000 Message-Id: <20230715150032.6917-1-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230715_080043_132069_30D7D6CE X-CRM114-Status: GOOD ( 16.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series provides support for running Vector code in kernel mode. The implementation is based on the v12 series of the Vector series, but with some additions. First, we introduce a mechanism to defer restoring Vector context for userspace programs (patch 1). This is similar to arm64 and x86's approaches when dealing with extra userspace register context. And it is benefitial to both Vector in user and kernel-mode. Then, patch 2, 3 add the kernel-mode Vector patch from v12 with minor modifications. At the end of the series, patch 4, 5, 6 add supports for making kernel-mode Vector code preemptible. We do this by adding kernel-mode Vector context, and keeping track of the frame where V context is last valid. We believe that enabling preemption of running V is a critical path for getting V more generally available in the kernel-mode. Besides, with status.VS, we can easily tell if saving/restoring V is required. This reduce the level of cost when running SIMD in kernel mode as compared to other arches. Other arches usually do not have a way to tell if extra context is dirty. Thus, if they also want to support running preemptible code with extra registers, then they must save/restore extra context at each context switch even if registers are not dirty. The series is tested by loading a kernel module on a preemptive kernel. The module launches multiple kworkers which run Vector operations and verifies with scalar code. Also, the module provides userspace intefaces via fops to verify if we can run Vector code on syscall path. Changes from the vector v12 series (for patch 2, 3): - return a failure code when kernel_rvv_begin() fails. - Do not immediately restore user's V context. Andy Chiu (4): riscv: sched: defer restoring Vector context for user riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}() riscv: vector: allow kernel-mode Vector with preemption riscv: vector: enable preemptive kernel-mode Vector to be built Greentime Hu (2): riscv: Add support for kernel mode vector riscv: Add vector extension XOR implementation arch/riscv/Kconfig | 10 ++ arch/riscv/include/asm/entry-common.h | 13 ++ arch/riscv/include/asm/processor.h | 2 + arch/riscv/include/asm/thread_info.h | 6 + arch/riscv/include/asm/vector.h | 50 +++++-- arch/riscv/include/asm/xor.h | 82 +++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/asm-offsets.c | 2 + arch/riscv/kernel/entry.S | 41 ++++++ arch/riscv/kernel/kernel_mode_vector.c | 180 +++++++++++++++++++++++++ arch/riscv/kernel/process.c | 10 +- arch/riscv/kernel/ptrace.c | 2 +- arch/riscv/kernel/signal.c | 4 +- arch/riscv/kernel/vector.c | 5 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 +++++++++++ 16 files changed, 473 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/kernel/kernel_mode_vector.c create mode 100644 arch/riscv/lib/xor.S Tested-by: Heiko Stuebner