mbox series

[v6,00/10] riscv: Allow userspace to directly access perf counters

Message ID 20230802080328.1213905-1-alexghiti@rivosinc.com (mailing list archive)
Headers show
Series riscv: Allow userspace to directly access perf counters | expand

Message

Alexandre Ghiti Aug. 2, 2023, 8:03 a.m. UTC 
riscv used to allow direct access to cycle/time/instret counters,
bypassing the perf framework, this patchset intends to allow the user to
mmap any counter when accessed through perf.

**Important**: The default mode is now user access through perf only, not
the legacy so some applications will break. However, we introduce a sysctl
perf_user_access like arm64 does, which will allow to switch to the legacy
mode described above.

This version needs openSBI v1.3 *and* a kernel fix that went upstream lately
(https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/).

base-commit-tag: v6.5-rc1

Changes in v6:
- Replaced csr_read() preprocessor parsing of csr number with the
  input constraint, as suggested by Ian
- Added a defined(__riscv) and a comment to make things clearer, as
  suggested by Ian

Changes in v5:
- Fix typo from Atish
- Add RB from Atish and Andrew
- Improve cover letter and patch 7 commit log to explain why we made the
  choice to break userspace for security reasons, thanks Atish and Rémi
- Rebase on top of v6.5-rc1

Changes in v4:
- Fixed some nits in riscv_pmu_sbi.c thanks to Andrew
- Fixed the documentation thanks to Andrew
- Added RB from Andrew \o/

Changes in v3:
- patch 1 now contains the ref to the faulty commit (no Fixes tag as it is only a comment), as Andrew suggested
- Removed RISCV_PMU_LEGACY_TIME from patch 3, as Andrew suggested
- Rename RISCV_PMU_PDEV_NAME to "riscv-pmu-sbi", patch4 is just cosmetic now, as Andrew suggested
- Removed a few useless (and wrong) comments, as Andrew suggested
- Simplify arch_perf_update_userpage code, as Andrew suggested
- Documentation now mentions that time CSR is *always* accessible, whatever the mode, as suggested by Andrew
- Removed CYCLEH reference and add TODO for rv32 support, as suggested by Atish
- Do not rename the pmu instance as Atish suggested
- Set pmc_width only if rdpmc is enabled and CONFIG_RISCV_PMU is set and the event is a hw event
- Move arch_perf_update_userpage https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/
- **Switch to user mode access by default**

Changes in v2:
- Split into smaller patches, way better!
- Add RB from Conor
- Simplify the way we checked riscv architecture
- Fix race mmap and other thread running on other cpus
- Use hwc when available
- Set all userspace access flags in event_init, too cumbersome to handle sysctl changes
- Fix arch_perf_update_userpage for pmu other than riscv-pmu by renaming pmu driver
- Fixed kernel test robot build error
- Fixed documentation (Andrew and Bagas)
- perf testsuite passes mmap tests in all 3 modes

Alexandre Ghiti (10):
  perf: Fix wrong comment about default event_idx
  include: riscv: Fix wrong include guard in riscv_pmu.h
  riscv: Make legacy counter enum match the HW numbering
  drivers: perf: Rename riscv pmu sbi driver
  riscv: Prepare for user-space perf event mmap support
  drivers: perf: Implement perf event mmap support in the legacy backend
  drivers: perf: Implement perf event mmap support in the SBI backend
  Documentation: admin-guide: Add riscv sysctl_perf_user_access
  tools: lib: perf: Implement riscv mmap support
  perf: tests: Adapt mmap-basic.c for riscv

 Documentation/admin-guide/sysctl/kernel.rst |  27 ++-
 drivers/perf/riscv_pmu.c                    | 113 +++++++++++
 drivers/perf/riscv_pmu_legacy.c             |  28 ++-
 drivers/perf/riscv_pmu_sbi.c                | 196 +++++++++++++++++++-
 include/linux/perf/riscv_pmu.h              |  12 +-
 include/linux/perf_event.h                  |   3 +-
 tools/lib/perf/mmap.c                       |  66 +++++++
 tools/perf/tests/mmap-basic.c               |   6 +-
 8 files changed, 431 insertions(+), 20 deletions(-)

Comments

patchwork-bot+linux-riscv@kernel.org Aug. 30, 2023, 1:20 p.m. UTC | #1 
Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Wed,  2 Aug 2023 10:03:18 +0200 you wrote:
> riscv used to allow direct access to cycle/time/instret counters,
> bypassing the perf framework, this patchset intends to allow the user to
> mmap any counter when accessed through perf.
> 
> **Important**: The default mode is now user access through perf only, not
> the legacy so some applications will break. However, we introduce a sysctl
> perf_user_access like arm64 does, which will allow to switch to the legacy
> mode described above.
> 
> [...]

Here is the summary with links:
  - [v6,01/10] perf: Fix wrong comment about default event_idx
    https://git.kernel.org/riscv/c/366d259ff597
  - [v6,02/10] include: riscv: Fix wrong include guard in riscv_pmu.h
    https://git.kernel.org/riscv/c/f117ae55b019
  - [v6,03/10] riscv: Make legacy counter enum match the HW numbering
    https://git.kernel.org/riscv/c/e8b785e98abb
  - [v6,04/10] drivers: perf: Rename riscv pmu sbi driver
    https://git.kernel.org/riscv/c/d5ac062d82d8
  - [v6,05/10] riscv: Prepare for user-space perf event mmap support
    https://git.kernel.org/riscv/c/83c5e13b8cbb
  - [v6,06/10] drivers: perf: Implement perf event mmap support in the legacy backend
    https://git.kernel.org/riscv/c/50be34282905
  - [v6,07/10] drivers: perf: Implement perf event mmap support in the SBI backend
    https://git.kernel.org/riscv/c/cc4c07c89aad
  - [v6,08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access
    https://git.kernel.org/riscv/c/57972127b20e
  - [v6,09/10] tools: lib: perf: Implement riscv mmap support
    https://git.kernel.org/riscv/c/60bd50116484
  - [v6,10/10] perf: tests: Adapt mmap-basic.c for riscv
    https://git.kernel.org/riscv/c/26ba042414a3

You are awesome, thank you!